C8051T600QDB Silicon Laboratories Inc, C8051T600QDB Datasheet - Page 152
![BOARD SOCKET DAUGHTER QFN](/photos/9/3/90365/c8051t600qdb_sml.jpg)
C8051T600QDB
Manufacturer Part Number
C8051T600QDB
Description
BOARD SOCKET DAUGHTER QFN
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T600QDB
Module/board Type
Socket Module - QFN
Data Bus Width
8 bit
Operating Supply Voltage
+ 1.8 V to + 3.6 V
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051T600DK
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1406
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C8051T600/1/2/3/4/5/6
SFR Definition 25.3. TMOD: Timer Mode
SFR Address = 0x89
152
Name
Reset
5:4
1:0
Bit
Type
7
6
3
2
Bit
T1M[1:0]
T0M[1:0]
GATE1
GATE0
Name
C/T1
C/T0
GATE1
R/W
7
0
Timer 1 Gate Control.
0: Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level.
1: Timer 1 enabled only when TR1 = 1 AND INT1 is active as defined by bit IN1PL in
register IT01CF (see SFR Definition 17.5).
Counter/Timer 1 Select.
0: Timer: Timer 1 incremented by clock defined by T1M bit in register CKCON.
1: Counter: Timer 1 incremented by high-to-low transitions on external pin (T1).
Timer 1 Mode Select.
These bits select the Timer 1 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Timer 1 Inactive
Timer 0 Gate Control.
0: Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level.
1: Timer 0 enabled only when TR0 = 1 AND INT0 is active as defined by bit IN0PL in
register IT01CF (see SFR Definition 17.5).
Counter/Timer 0 Select.
0: Timer: Timer 0 incremented by clock defined by T0M bit in register CKCON.
1: Counter: Timer 0 incremented by high-to-low transitions on external pin (T0).
Timer 0 Mode Select.
These bits select the Timer 0 operation mode.
00: Mode 0, 13-bit Counter/Timer
01: Mode 1, 16-bit Counter/Timer
10: Mode 2, 8-bit Counter/Timer with Auto-Reload
11: Mode 3, Two 8-bit Counters/Timers
C/T1
R/W
6
0
5
0
T1M[1:0]
R/W
Rev. 1.2
4
0
Function
GATE0
R/W
3
0
C/T0
R/W
2
0
1
0
T0M[1:0]
R/W
0
0
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