KSZ8851SNL-BBE-EVAL Micrel Inc, KSZ8851SNL-BBE-EVAL Datasheet - Page 60

• Manufacturer Part Number: KSZ8851SNL-BBE-EVAL
• Description: BOARD EVAL MAC/PHY FOR KSZ8851
• Manufacturer: Micrel Inc
• Series: LinkMD®r

Specifications of KSZ8851SNL-BBE-EVAL

• Design Resources: BeagleBoard Zippy2
• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8851SNL
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: SPI Interface, LinkMD Cable Diagnostics
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3602; KSZ8851SNL-BBE-EVL; ZIPPY2

0xCA – 0xCF: Reserved
Indirect Access Data Low Register (0xD0 – 0xD1): IADLR
This register contains the indirect data (low word) for MIB counter.
Indirect Access Data High Register (0xD2 – 0xD3): IADHR
This register contains the indirect data (high word) for MIB counter.
Power Management Event Control Register (0xD4 – 0xD5): PMECR
This register is used to control the KSZ8851SNL power management event, capabilities and status.
August 2009
Micrel, Inc.
Bit
15-13
12
11-10
9-5
4-0
Bit
15-0
Bit
15-0
Bit
15
14
13
12
11-8
Default Value
-
0
0
0
0x0
0x0
-
Default
0x0
0x0
0x00
Default
0x0000
Default
0x0000
R/W
RW
RW
RW
RW
RW
R/W
RW
R/W
RW
R/W
RO
RW
RW
RW
RW
Description
Reserved.
Read Enable
1 = Read cycle is enabled (MIB counter will clear after read).
0 = No operation.
Table Select
00 = reserved.
01 = reserved.
10 = reserved.
11 = MIB counter selected.
Reserved
Indirect Address
Bit 4-0 of indirect address for 32 MIB counter locations.
Description
Indirect Low Word Data
Bit 15-0 of indirect data.
Description
Indirect High Word Data
Bit 31-16 of indirect data.
Description
Reserved
PME Delay Enable
This bit is used to enable the delay of PME output pin 2 assertion.
When this bit is set to 1, the device will not assert the PME output till the device’s all
clocks are running and ready for host access.
When this bit is set to 0, the device will assert the PME output without delay.
This bit is only valid when Auto Wake-Up Enable (bit7) is set to 1 in this register.
Reserved
PME Output Polarity
This bit is used to control the PME output pin 2 polarity.
When this bit is set to 1, the PME output pin 2 is active high.
When this bit is set to 0, the PME output pin 2 is active low.
Wake-on-LAN to PME Output Enable
These four bits are used to enable the PME output pin 2 asserted when one of these
wake-on-LAN events is detected:
Bit 11: is corresponding to receive wake-up frame.
Bit 10: is corresponding to receive magic packet.
Bit 9: is corresponding to link change from down to up.
60
KSZ8851SNL/SNLI
M9999-083109-2.0