CDB5463U Cirrus Logic Inc, CDB5463U Datasheet - Page 8

• Manufacturer Part Number: CDB5463U
• Description: BOARD EVAL & SOFTWARE CS5463 ADC
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5463U

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5463
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI Interfaces
• Product: Data Conversion Development Tools
• Maximum Clock Frequency: 4 MHz
• Interface Type: USB
• Supply Voltage (max): 5 V
• Supply Voltage (min): 3.3 V
• For Use With/related Products: CS5463
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1553

ANALOG CHARACTERISTICS
Notes: 3. Applies before system calibration.
8
Analog Inputs (Voltage Channel)
Differential Input Range
Total Harmonic Distortion
Crosstalk with Current Channel at Full Scale (50, 60 Hz)
Input Capacitance
Effective Input Impedance
Noise (Referred to Input)
Offset Drift (Without the High Pass Filter)
Gain Error
Temperature Channel
Temperature Accuracy
Power Supplies
Power Supply Currents (Active State)
Power Consumption
(Note 4)
Power Supply Rejection Ratio
(Note 5)
PFMON Low-voltage Trigger Threshold
PFMON High-voltage Power-on Trip Point
4. All outputs unloaded. All inputs CMOS level.
5. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV
6. When voltage level on PFMON is sagging, and LSD bit = 0, the voltage at which LSD is set to 1.
7. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on
(zero-to-peak) (60 Hz) sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The
“+” and “-” input pins of both input channels are shorted to AGND. Then the CS5463 is commanded to
continuous conversion acquisition mode, and digital output data is collected for the channel under test.
The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted
into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined
as Veq. PSRR is then (in dB)
PFMON at which the LSD bit can be permanently reset back to 0.
Active State (VA+ = 5 V, VD+ = 3.3 V)
Parameter
Active State (VA+ = VD+ = 5 V)
I
D+
(VA+ = 5 V, VD+ = 3.3 V)
I
D+
(VA+ = VD+ = 5 V)
Voltage Channel
Current Channel
All Gain Ranges
:
[(VIN+) - (VIN-)]
(Continued)
Stand-by State
Sleep State
(50, 60 Hz)
PSRR
(Note 3)
(Note 6)
(Note 7)
=
I
A+
20
⋅
log
Symbol
PSCA
PSCD
PSCD
PSRR
PMLO
PMHI
THD
VIN
OD
GE
PC
EII
N
IC
150
--------- -
V
T
V
eq
Min
2.3
65
45
70
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
16.0
2.55
±3.0
11.6
2.45
Typ
500
140
-70
0.2
1.1
2.9
1.7
75
±5
21
10
65
75
8
-
-
Max
17.5
2.7
29
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CS5463
DS678F2
mV
µV/°C
µV
Unit
mW
mW
mW
MΩ
mA
mA
mA
µW
dB
dB
pF
°C
dB
dB
%
V
V
rms
P-P