ADCLK950/PCBZ Analog Devices Inc, ADCLK950/PCBZ Datasheet - Page 11

BOARD EVALUATION FOR ADCLK950

ADCLK950/PCBZ

Manufacturer Part Number
ADCLK950/PCBZ
Description
BOARD EVALUATION FOR ADCLK950
Manufacturer
Analog Devices Inc
Series
SIGer
Datasheets

Specifications of ADCLK950/PCBZ

Main Purpose
Timing, Clock Buffer / Driver / Receiver / Translator
Utilized Ic / Part
ADCLK950
Primary Attributes
2 Selectable Inputs, 10 Outputs
Secondary Attributes
LVPECL Output Logic
Silicon Manufacturer
Analog Devices
Application Sub Type
Clock Fanout Buffer
Kit Application Type
Clock & Timing
Silicon Core Number
ADCLK950
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Embedded
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
INPUT TERMINATION OPTIONS
Figure 20. DC-Coupled LVPECL Input Termination
Figure 19. DC-Coupled CML Input Termination
(OPTIONAL)
V
0.01µF
CONNECT V
CC
50Ω
V
CC
V
CLKx
CLKx
50Ω
ADCLK950
T
T
x
x TO V
V
CLKx
CLKx
V
ADCLK950
T
50Ω
REF
x
CC
50Ω
.
x
V
REF
50Ω
x
Rev. A | Page 11 of 12
Figure 21. AC-Coupled Input Termination, Such as LVDS and LVPECL
Figure 22. AC-Coupled Single-Ended Input Termination
Figure 23. DC-Coupled 3.3 V CMOS Input Termination
CONNECT V
BYPASS CAPACITOR FROM V
ALTERNATIVELY, V
CONNECTED, GIVING A CLEANER LAYOUT AND
A 180º PHASE SHIFT.
CONNECT V
T
x, V
V
CLKx
CLKx
V
CLKx
CLKx
REF
50Ω
ADCLK950
ADCLK950
T
50Ω
V
CLKx
CLKx
50Ω
T
x
ADCLK950
T
T
x
T
x
x TO V
x, AND CLKx. PLACE A
x, V
V
V
REF
REF
V
REF
REF
REF
x, AND CLKx CAN BE
50Ω
x
50Ω
x
50Ω
x
T
x.
x TO GROUND.
ADCLK950

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