CDB42428 Cirrus Logic Inc, CDB42428 Datasheet - Page 42

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CDB42428

Manufacturer Part Number
CDB42428
Description
BOARD EVAL FOR CS42428 CODEC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB42428

Main Purpose
Audio, CODEC
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
CS42428/26/18/16
Primary Attributes
6 Single-Ended Analog Inputs and 8 Outputs, S/PDIF Digital Audio Transmitter and Receiver
Secondary Attributes
Graphic User Interface
Product
Audio Modules
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1499
42
6. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock Status
and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment informa-
tion. The default state of each bit after a power-up sequence or reset is listed in each bit description.
6.1
6.1.1
6.1.2
6.2
6.2.1
6.2.2
Chip_ID3
INCR
7
7
Memory Address Pointer (MAP)
INCREMENT (INCR)
MEMORY ADDRESS POINTER (MAPX)
Chip I.D. and Revision Register (address 01h) (Read Only)
CHIP I.D. (CHIP_IDX)
CHIP REVISION (REV_IDX)
Not a register
Default = 1
Function:
Default = 0000001
Function:
Default = 1111
Function:
Default = xxxx
Function:
Memory Address Pointer auto increment control
Memory Address Pointer (MAP). Sets the register address that will be read or written by the control
port.
I.D. code for the CS42428. Permanently set to 1111.
CS42428 revision level.
Revision C1 is coded as 0101
Revision C is coded as 0011.
Chip_ID2
MAP6
0 -
1 -
6
6
Chip_ID1
MAP5
MAP is not incremented automatically.
Internal MAP is automatically incremented after each read or write.
5
5
CHIP_ID0
MAP4
4
4
Rev_ID3
MAP3
3
3
Rev_ID2
MAP2
2
2
Rev_ID1
MAP1
1
1
CS42428
Rev_ID0
MAP0
DS605F1
0
0

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