AD8153-EVALZ Analog Devices Inc, AD8153-EVALZ Datasheet
AD8153-EVALZ
Specifications of AD8153-EVALZ
Related parts for AD8153-EVALZ
AD8153-EVALZ Summary of contents
Page 1
... The device has unicast and bicast capability capable of supporting either 1:1 redundancy. Using a mixture of bicast and loopback modes, the AD8153 can also be used to test high speed serial links by duplicating the incoming data and transmitting it to the destination port and test equipment simultaneously ...
Page 2
... Receive Equalization .................................................................. 14 REVISION HISTORY 4/07—Revision 0: Initial Version. Transmit Pre-Emphasis ............................................................. Serial Control Interface........................................................... 15 Register Set.................................................................................. 15 General Functionality ................................................................ Data Write............................................................................. Data Read.............................................................................. 17 Applications Information .............................................................. 18 PCB Design Guidelines ................................................................. 19 Interfacing to the AD8153............................................................. 20 Termination Structures.............................................................. 20 Input Compliance....................................................................... 20 Output Compliance ................................................................... 21 Outline Dimensions ....................................................................... 22 Ordering Guide .......................................................................... 22 Rev Page ...
Page 3
... Still air JA LOGIC INPUT CHARACTERISTICS Input High ( Input Low ( Input differential voltage swing Ω, two outputs active with no pre-emphasis, data rate = 3.2 Gbps, ac-coupled, PRBS7 test 1 = 800 mV p Rev Page AD8153 Min Typ Max Unit DC 3.2 Gbps 16 ps p-p 500 fs 640 200 ...
Page 4
... AD8153 TIMING SPECIFICATIONS SDA LOW SCL t HD;STA t HD;DAT S Table 2. Parameter SCL Clock Frequency Hold Time for a Start Condition Set-up Time for a Repeated Start Condition Low Period of the SCL Clock High Period of the SCL Clock Data Hold Time Data Set-Up Time Rise Time for Both SDA and SCL ...
Page 5
... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. < 0 ESD CAUTION Rev Page AD8153 ...
Page 6
... OPC 29 PE_A/(I2C_A[0]) 30 INC 31 IPC VCC 1 24 MODE PIN 1 VTTO 2 23 RESETB INDICATOR ONA 3 22 SEL AD8153 OPA 4 21 BICAST VTTI 5 20 LB_A TOP VIEW INA 6 19 LB_B IPA 7 18 LB_C VEE 8 17 EQ_A/(SCL) NOTE EPAD NEEDS TO BE ELECTRICALLY CONNECTED TO VEE. ...
Page 7
... A 50Ω CABLES 50Ω CABLES INPUT OUTPUT PIN PIN AD8153 AC COUPLED TP1 EVALUATION BOARD Figure 4. Standard Test Circuit (No Channel) Rev Page AD8153 2 50Ω HIGH-SPEED SAMPLING TP2 OSCILLOSCOPE 40ps/DIV Figure 6. 3.2 Gbps Output Eye, No Channel (TP2 from Figure 4) ...
Page 8
... Figure 10. 3.2 Gbps Output Eye, 20 Inch FR4 Input Channel, High EQ Figure 11. 3.2 Gbps Output Eye, 40 Inch FR4 Input Channel, High EQ Rev Page 50Ω CABLES INPUT OUTPUT PIN PIN 50Ω HIGH- AD8153 SPEED AC COUPLED TP2 TP3 SAMPLING EVALUATION OSCILLOSCOPE BOARD 40ps/DIV (TP3 from Figure 7) 40ps/DIV (TP3 from Figure 7) ...
Page 9
... AC COUPLED TP1 TP2 EVALUATION BOARD Figure 12. Output Pre-Emphasis Test Circuit Figure 15. 3.2 Gbps Output Eye, 20 Inch FR4 Output Channel Figure 16. 3.2 Gbps Output Eye, 40 Inch FR4 Output Channel Rev Page AD8153 50Ω CABLES 2 2 FR4 TEST BACKPLANE 50Ω HIGH- DIFFERENTIAL SPEED ...
Page 10
... AD8153 LOW HIGH FR4 INPUT CHANNEL LENGTH (IN) Figure 17. Deterministic Jitter vs. FR4 Input Channel Length DETERMINISTIC JITTER RANDOM JITTER 0 1.0 1.5 2.0 2.5 DATA RATE (Gbps) Figure 18. Jitter vs. Data Rate DETERMINISTIC JITTER 20 10 RANDOM JITTER 0 0 0.2 0.4 0.6 0.8 1.0 1.2 DIFFERENTIAL INPUT SWING (V) Figure 19 ...
Page 11
... Figure 26. Jitter vs. Output Termination Voltage 100 –40 80 100 700 650 600 550 500 –40 3.5 3.6 Figure 28. Propagation Delay vs. Temperature Rev Page AD8153 DETERMINISTIC JITTER RANDOM JITTER 2.2 2.4 2.6 2.8 3.0 3.2 3.4 VTTO (V) – TEMPERATURE (°C) Figure 27. Rise/Fall Time vs. Temperature –20 ...
Page 12
... AD8153 1000 900 800 700 600 500 400 300 200 100 0 3.0 3.1 3.2 3.3 V (V) CC Figure 29. Eye Height vs. Core Supply Voltage 3.4 3.5 3.6 Rev Page 1000 900 800 700 600 500 400 300 200 100 0 0 0.5 1.0 1.5 2 ...
Page 13
... THEORY OF OPERATION The AD8153 consists of a 2:1 multiplexer and a 1:2 demultiplexer. There are three operating modes: pin mode, serial mode, and mixed mode. In pin mode, lane switching, equalization, and pre-emphasis are controlled using external pins. In serial mode interface is used to control the device and to provide access to advanced features, such as additional pre-emphasis settings and output disable ...
Page 14
... RECEIVE EQUALIZATION In backplane applications, the AD8153 needs to compensate for signal degradation caused by long traces. The device supports two levels of input equalization, configured on a per-port basis. Table 6 summarizes the high-frequency asymptotic gain boost for each setting. Table 6. Receive Equalization Settings EQ_A/B/C EQ Boost ...
Page 15
... I C SERIAL CONTROL INTERFACE REGISTER SET The AD8153 can be controlled in one of three modes: pin mode, serial mode, and mixed mode. In pin mode, the AD8153 control is derived from the package pins, whereas in serial mode a set of internal registers controls the AD8153. There is also a mixed mode where switching is controlled via external pins, and equalization and pre-emphasis are controlled via the internal registers ...
Page 16
... I2C_ADDR bits are set to b011. In Figure 32, the corresponding step number is visible in the circle under the waveform. The SCL line is driven by the I by the AD8153 slave. As for the SDA line, the data in the shaded polygons is driven by the AD8153, whereas the data in the non- shaded polygons is driven by the I shown is that of 9a ...
Page 17
... In the example, Data 0x49 is read from Address 0x6D of an AD8153 part with a part address of 0x4B. The part address is seven bits wide and is composed of the AD8153 static upper four bits (b1001) and the pin programmable lower three bits (I2C_ADDR[2:0]) ...
Page 18
... The device can be configured to support either 1:1 redundancy. PHYSICAL INTERFACE PHYSICAL INTERFACE Another application for the AD8153 is in test equipment for evaluating high speed serial links. Figure 36 illustrates a possible application of the AD8153 in a simple link tester. DIGITAL ENGINE AD8153 LINE CARDS ...
Page 19
... The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE Rev Page AD8153 ...
Page 20
... TERMINATION STRUCTURES To determine the best strategy for connecting to the high speed pins of the AD8153, the user must first be familiar with the on- chip termination structures. The AD8153 contains two types of these structures: one type for input ports and one type for output ports (see Figure 37 and Figure 38) ...
Page 21
... OUTPUT COMPLIANCE Figure graphical depiction of the single-ended waveform at the output of the AD8153. The common-mode level (V and the amplitude ( this waveform are a function of the OSE output tail current (I ), the output termination supply voltage the topology of the far-end receiver, and whether ac- or TTO dc-coupling is used ...
Page 22
... TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE SLUG. ORDERING GUIDE Model Temperature Range AD8153ACPZ 1 −40°C to +85°C 1 AD8153ACPZ-RL7 −40°C to +85°C AD8153-EVALZ RoHS Compliant Part. 5.00 BSC SQ 0.60 MAX 24 0.50 TOP BSC 4.75 ...
Page 23
... NOTES Rev Page AD8153 ...
Page 24
... AD8153 NOTES ©2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06393-0-4/07(0) Rev Page ...