CP2400AB Silicon Laboratories Inc, CP2400AB Datasheet - Page 78

• Manufacturer Part Number: CP2400AB
• Description: BOARD EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400AB

• Main Purpose: LCD Development
• Embedded: No
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Accessories
• Core Processor: CP2400
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: CP2400
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1857

CP2400/1/2/3
1. Disable SmaRTClock Alarm Events (RTC0AEN = 0).
2. Set the ALARMn registers to the desired value.
3. Enable SmaRTClock Alarm Events (RTC0AEN = 1).
Notes: The ALRM bit, which is used as the SmaRTClock Alarm Event flag, is cleared by disabling SmaRTClock Alarm Events
11.3.3. Software Considerations for using the SmaRTClock Timer and Alarm
The SmaRTClock timer and alarm have two operating modes to suit varying applications. The two modes are
described below:
Mode 1:
The first mode uses the SmaRTClock timer as a perpetual timebase which is never reset to zero. Every 36 hours,
the timer is allowed to overflow without being stopped or disrupted. The alarm interval is software managed and is
added to the ALRMn registers by software after each alarm. This allows the alarm match value to always stay
ahead of the timer by one software managed interval. If software uses 32-bit unsigned addition to increment the
alarm match value, then it does not need to handle overflows since both the timer and the alarm match value will
overflow in the same manner.
This mode is ideal for applications which have a long alarm interval (e.g., 24 or 36 hours) and/or have a need for a
perpetual timebase. An example of an application that needs a perpetual timebase is one whose wake-up interval
is constantly changing. For these applications, software can keep track of the number of timer overflows in a 16-bit
variable, extending the 32-bit (36 hour) timer to a 48-bit (272 year) perpetual timebase.
Mode 2:
The second mode uses the SmaRTClock timer as a general purpose up counter which is auto reset to zero by
hardware after each alarm. The alarm interval is managed by hardware and stored in the ALRMn registers.
Software only needs to set the alarm interval once during device initialization. After each alarm, software should
keep a count of the number of alarms that have occurred in order to keep track of time.
This mode is ideal for applications that require minimal software intervention and/or have a fixed alarm interval.
This mode is the most power efficient since it requires less CPU time per alarm.
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(RTC0AEN = 0).
Disabling (RTC0AEN = 0) then re-enabling Alarm Events (RTC0AEN = 1) after a SmaRTClock Alarm without modifying
ALARMn registers will automatically schedule the next alarm after 2^32 SmaRTClock cycles (approximately 36 hours
using a 32.768 kHz crystal).
The SmaRTClock Alarm Event flag will remain asserted for a maximum of one SmaRTClock cycle. The Alarm Event
however will be captured by the interrupt logic and will post a non-transient interrupt.
Rev. 1.0