DP83848T-MAU-EK National Semiconductor, DP83848T-MAU-EK Datasheet
DP83848T-MAU-EK
Specifications of DP83848T-MAU-EK
Related parts for DP83848T-MAU-EK
DP83848T-MAU-EK Summary of contents
Page 1
... Access Control (MAC) clock source component. In addi- tion, both MII and RMII are supported ensuring ease and flexibility of design. The DP83848T is offered in a tiny 6mm x 6mm LLP 40- pin package and is ideal for industrial controls, build- ing/factory automation, transportation, test equipment and wireless base stations. ...
Page 2
... TX_CLK 10BASE-T & 100BASE-TX Transmit Block DAC Auto-MDIX www.national.com MII/RMII SERIAL MANAGEMENT MII/RMII INTERFACE MII Registers Auto-Negotiation State Machine Clock Generation TD± RD± REFERENCE CLOCK Figure 1. DP83848T Functional Block Diagram 2 RX_CLK RX_DATA 10BASE-T & 100BASE-TX Receive Block ADC LED Driver LED ...
Page 3
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 5
Mb/s MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 6
... Figure 1. DP83848T Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Figure 2. PHYAD Strapping Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 3. AN0 Strapping and LED Loading Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 4. Typical MDC/MDIO Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 5. Typical MDC/MDIO Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 6. 100BASE-TX Transmit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 7. 100BASE-TX Receive Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, 100, 130 & 150 meters of CAT 5 cable . . . . . 27 Figure 9 ...
Page 7
Table 1. Auto-Negotiation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 8
... TX_CLK TX_EN TXD_0 TXD_1 TXD_2 TXD_3 RESERVED RESERVED RESERVED Note: Die Attached Pad (DAP) provides thermal dissipation, connection to GND plane recommended. www.national.com DP83848T DAP 10 Top View Order Number DP83848T NS Package Number NSQAU040 8 30 PFBIN2 DGND IOVDD33 26 MDC 25 MDIO 24 RESET_N 23 LED_LINK/AN0 22 25MHz_OUT 21 ...
Page 9
... RX_CLK O RX_DV O, PD Note: Strapping pin option. Please see Section 1.61.6 for strap definitions. All DP83848T signal pins are I/O cells regardless of the particular use. The definitions below define the functionality of the I/O cells for each pin. Type: I Input Type: O Output ...
Page 10
... Pin # I 28 CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83848T and must be connected MHz 0.005% (+50 ppm) clock source. The DP83848T supports either an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. ...
Page 11
... Description 23 RESET: Active Low input that initializes or re-initializes the DP83848T. Asserting this pin low for at least 1 s will force a reset process to occur. All internal registers will re-initialize to their de- fault states as specified for each bit in the Register Block section. All strap options are re-initialized as well. ...
Page 12
... DP83848T according to the following table. The value on this pin is set by connecting it to GND ( tors. This pin should NEVER be connected directly to GND or VCC. The value set at this input is latched into the DP83848T at Hard- ware-Reset. The float/pull-down status of this pin is latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset ...
Page 13
Mb/s and 100 Mb/s PMD Interface Signal Name Type TD-, TD+ I/O RD-, RD+ I/O 1.8 Special Connections Signal Name Type RBIAS I PFBOUT O PFBIN1 I PFBIN2 RESERVED I/O 1.9 Power Supply Pins Signal Name IOVDD33 IOGND ...
Page 14
Package Pin Assignments NSQAU040 Pin # 1 IO_VDD 2 TX_CLK 3 TX_EN 4 TXD_0 5 TXD_1 6 TXD_2 7 TXD_3 8 RESERVED 9 RESERVED 10 RESERVED 11 RD- 12 RD+ 13 AGND ...
Page 15
... Auto-Negotiation ability, and Extended Register Capability. These bits are permanently set to indicate the full functionality of the DP83848T (only the 100BASE-T4 bit is not set since the DP83848T does not support that function). The BMSR also provides status on: — ...
Page 16
... FLP (Fast Link Pulse) bursts. www.national.com 2.1.5 Enabling Auto-Negotiation via Software It is important to note that if the DP83848T has been ini- tialized upon power- non-auto-negotiating device (forced technology), and it is then required that Auto- Negotiation or re-Auto-Negotiation be initiated via soft- ...
Page 17
... PHYAD3 39 PHYAD4 The DP83848T can be set to respond to any of 32 possible PHY addresses via strap pins. The information is latched into the PHYCR register (address 19h, bits [4:0]) at device power-up and hardware reset. The PHY Address pins are shared with the RXD and COL pins. Each DP83848T or port sharing an MDIO bus in a system must have a unique physical address ...
Page 18
... BLINK for Activity Figure 3. AN0 Strapping and LED Loading Example 2.4.2 LED Direct Control The DP83848T provides another option to directly control thel LED output through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to the LED. ...
Page 19
... Mb/s). 2.6 Internal Loopback The DP83848T includes a Loopback Test mode for facilitat- ing system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Reg- ister (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs ...
Page 20
... Collisions are reported by the COL signal on the MII. If the DP83848T is transmitting in 10 Mb/s mode when a collision is detected, the collision is not reported until seven bits have been received while in the collision state. This prevents a collision being reported incorrectly due to noise on the network ...
Page 21
... Figure 4 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the DP83848T (PHY) for a typical regis- ter read access. For write transactions, the station management entity writes data to the addressed DP83848T thus eliminating the requirement for MDIO Turnaround ...
Page 22
... MAC or other management controller) deter- mines that all PHYs in the system support Preamble Sup- pression by returning a one in this bit, then the station management entity need not generate preamble for each management transaction. The DP83848T requires a single initialization sequence of 32 bits of preamble following hardware/software reset. www.national.com Z Z ...
Page 23
... Binary to MLT-3 converter / Common Driver The bypass option for the functional blocks within the 100BASE-TX transmitter provides flexibility for applications where data conversion is not always required. The DP83848T implements the 100BASE-TX transmit state machine diagram as specified in the IEEE 802.3u Stan- dard, Clause 24. TX_CLK ...
Page 24
DATA CODES IDLE AND CONTROL CODES INVALID CODES Note: Control ...
Page 25
... NRZ data from the code-group encoder. The result is a scrambled data stream with sufficient randomization to decrease radiated emissions at certain frequencies by as much as 20 dB. The DP83848T uses the PHY_ID (pins PHYAD [4:0]) to set a unique seed value. 4.1.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and ...
Page 26
RX_DV/CRS RX_CLK RX_DATA VALID SSD DETECT www.national.com RXD[3:0] / RX_ER 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT DESCRAMBLER NRZI TO NRZ DECODER MLT-3 TO BINARY DECODER DIGITAL SIGNAL PROCESSOR ANALOG FRONT END RD Figure 7. 100BASE-TX Receive Block Diagram ...
Page 27
... Figure 8. EIA/TIA Attenuation vs. Frequency for 0, 50, tive to ensure proper conditioning of the received signal independent of the cable length. The DP83848T utilizes an extremely robust equalization scheme referred as ‘Digital Adaptive Equalization.’ The Digital Equalizer removes ISI (inter symbol interfer- ence) from the receive data stream by continuously adapt- ing to provide a filter with the inverse frequency response of the channel ...
Page 28
... Standard for both voltage thresholds and timing parameters. Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-Negotiation by the 100BASE-TX receiver do not cause the DP83848T to assert signal detect. www.national.com Figure 9. 100BASE-TX BLW Event 4.2.4 MLT-3 to NRZI Decoder The DP83848T decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data ...
Page 29
... In Half Duplex mode the DP83848T functions as a stan- dard IEEE 802.3 10BASE-T transceiver supporting the CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83848T is capable of simulta- neously transmitting and receiving without asserting the collision signal. The DP83848T's 10 Mb/s ENDEC is designed to encode and decode simultaneously. ...
Page 30
... Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs. The DP83848T implements an intelligent receive squelch to ensure that impulse noise on the receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the 10BASE-T operational mode. ...
Page 31
... Transmit and Receive Filtering External 10BASE-T filters are not required when using the DP83848T, as the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resis- tors are required for the 10BASE-T transmit and receive interface ...
Page 32
Design Guidelines 5.1 TPI Network Circuit Figure 11 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers important that the user realize that variations with ...
Page 33
... After the system is assembled, internal compo- nents are less sensitive from ESD events. See Section 8.0 for ESD rating. 5.3 Clock In (X1) Recommendations The DP83848T supports an external CMOS level oscillator source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating ...
Page 34
Parameter Min Frequency Frequency Tolerance Frequency Stability Rise / Fall Time Jitter Jitter Symmetry 40% 1. This limit is provided as a guideline for component selection and not guaranteed by production testing. Refer to AN-1548, “PHYTER 100 Base-TX Reference Clock ...
Page 35
... BMCR (0x00h). 5.6 Energy Detect Mode When Energy Detect is enabled and there is no activity on the cable, the DP83848T will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848T to go through a normal power up sequence. Regardless of cable activity, the DP83848T will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible ...
Page 36
Register Block Offset Access Hex Decimal 00h 0 RW 01h 1 RO 02h 2 RO 03h 3 RO 04h 4 RW 05h 5 RW 05h 5 RW 06h 6 RW 07h 7 RW 08h-Fh 8-15 RW 10h 16 RO ...
Page 37
37 www.national.com ...
Page 38
www.national.com 38 ...
Page 39
Register Definition In the register definitions under the ‘Default’ heading, the following definitions hold true: — RW=Read Write access SC — =Register sets on event occurrence and Self-Clears when event ends — RW/SC =Read Write access/Self Clearing bit — ...
Page 40
Basic Mode Control Register (BMCR) Table 12. Basic Mode Control Register (BMCR), address 0x00 Bit Bit Name 15 Reset 14 Loopback 13 Speed Selection 12 Auto-Negotiation Enable 11 Power Down 10 Isolate 9 Restart Auto- Negotiation 8 Duplex Mode ...
Page 41
Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued) Bit Bit Name Default 7 Collision Test 6:0 RESERVED 7.1.2 Basic Mode Status Register (BMSR) Table 13. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name 15 100BASE-T4 14 ...
Page 42
Table 13. Basic Mode Status Register (BMSR), address 0x01 (Continued) Bit Bit Name 1 Jabber Detect 0 Extended Capability www.national.com Default 0, RO/LH Jabber Detect: This bit only has meaning in 10 Mb/s mode Jabber condition detected. 0 ...
Page 43
... The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848T. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management ...
Page 44
Table 16. Negotiation Advertisement Register (ANAR), address 0x04 (Continued) Bit Bit Name 11 ASM_DIR 10 PAUSE TX_FD 10_FD 5 10 4:0 Selector www.national.com Default 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ...
Page 45
Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 17. Auto-Negotiation Link Partner Ability ...
Page 46
Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 18. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 0x05 Bit Bit Name ACK ACK2 11 Toggle 10:0 CODE 7.1.8 Auto-Negotiate Expansion Register ...
Page 47
Table 19. Auto-Negotiate Expansion Register (ANER), address 0x06 (Continued) Bit Bit Name 0 LP_AN_ABLE 7.1.9 Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 20. ...
Page 48
Extended Registers 7.2.1 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 21. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name 15 RESERVED 14 MDI-X ...
Page 49
Table 21. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default 5 Jabber Detect Auto-Neg Complete Loopback Status Duplex Status Speed Status Link ...
Page 50
False Carrier Sense Counter Register (FCSCR) This counter provides information required to implement the “False Carriers” attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification. Table 22. False Carrier Sense Counter Register (FCSCR), ...
Page 51
Mb/s PCS Configuration and Status Register (PCSR) Table 24. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16 Bit Bit Name 15:13 RESERVED 12 RESERVED 11 RESERVED 10 TQ_EN 9 SD FORCE PMA 8 SD_OPTION 7 DESC_TIME ...
Page 52
RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 25. RMII and Bypass Register (RBR), addresses 0x17 Bit Bit Name 15:6 RESERVED 5 RMII_MODE ...
Page 53
LED Direct Control Register (LEDCR) This register provides the ability to directly control the LED output. It does not provide read access to the LED. Table 26. LED Direct Control Register (LEDCR), address 0x18 Bit Bit Name 15:6 RESERVED ...
Page 54
PHY Control Register (PHYCR) Table 27. PHY Control Register (PHYCR), address 0x19 Bit Bit Name 15 MDIX_EN 14 FORCE_MDIX 13 PAUSE_RX 12 PAUSE_TX 11 BIST_FE 10 PSR_15 9 BIST_STATUS 8 BIST_START 7 BP_STRETCH 6 RESERVED www.national.com Default Strap, RW ...
Page 55
Table 27. PHY Control Register (PHYCR), address 0x19 (Continued) Bit Bit Name Default 5 LED_CNFG[0] Strap, RW 4:0 PHYADDR[4:0] Strap, RW Description LED Configuration LED_ CNFG[0] Mode Description 1 Mode 1 0 Mode2 In Mode 1, LEDs are configured as ...
Page 56
Status/Control Register (10BTSCR) Table 28. 10Base-T Status/Control Register (10BTSCR), address 0x1A Bit Bit Name 15 RESERVED 14:12 RESERVED 11:9 SQUELCH 8 LOOPBACK_10_D IS 7 LP_DIS 6 FORCE_LINK_10 5 RESERVED 4 POLARITY 3 RESERVED 2 RESERVED 1 HEARTBEAT_DIS 0 ...
Page 57
CD Test and BIST Extensions Register (CDCTRL1) Table 29. CD Test and BIST Extensions Register (CDCTRL1), address 0x1B Bit Bit Name 15:8 BIST_ERROR_CO UNT 7:6 RESERVED 5 BIST_CONT_MOD E 4 CDPATTEN_10 3 RESERVED 2 10MEG_PATT_GA P 1:0 CDPATTSEL[1:0] Default ...
Page 58
Energy Detect Control (EDCR) Table 30. Energy Detect Control (EDCR), address 0x1D Bit Bit Name 15 ED_EN 14 ED_AUTO_UP 13 ED_AUTO_DOWN 12 ED_MAN 11 ED_BURST_DIS 10 ED_PWR_STATE 9 ED_ERR_MET 8 ED_DATA_MET 7:4 ED_ERR_COUNT 3:0 ED_DATA_COUNT www.national.com Default 0, RW ...
Page 59
Electrical Specifications Note: All parameters are guaranteed by test, statistical analysis or design. Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Storage Temperature (T ) STG Max ...
Page 60
Symbol Pin Types Parameter C I CMOS Input IN1 Capacitance C O CMOS Output OUT1 Capacitance SD PMD Input 100BASE-TX THon Pair Signal detect turn- on threshold SD PMD Input 100BASE-TX THoff Pair Signal detect turn- off threshold V PMD ...
Page 61
AC Specs 8.2.1 Power Up Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.1.1 Post Power Up Stabilization time prior to MDC preamble for register accesses ...
Page 62
Reset Timing Vcc X1 clock Hardware RESET_N MDC Latch-In of Hardware Configuration Pins Dual Function Pins Become Enabled As Outputs Parameter Description T2.2.1 Post RESET Stabilization time prior to MDC preamble for reg- ister accesses T2.2.2 Hardware Configuration Latch- ...
Page 63
MII Serial Management Timing MDC MDIO (output) MDC MDIO (input) Parameter Description T2.3.1 MDC to MDIO (Output) Delay Time T2.3.2 MDIO (Input) to MDC Setup Time T2.3.3 MDIO (Input) to MDC Hold Time T2.3.4 MDC Frequency 8.2.4 100 Mb/s ...
Page 64
Mb/s MII Receive Timing RX_CLK T2.5.2 RXD[3:0] RX_DV RX_ER Parameter Description T2.5.1 RX_CLK High/Low Time T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode Note: RX_CLK may be held low or high for a longer period ...
Page 65
Transmit Packet Deassertion Timing TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.7.1 TX_CLK to PMD Output Pair Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deasser- ...
Page 66
Transmit Timing (t PMD Output Pair T2.8.2 PMD Output Pair eye pattern Parameter Description T2.8.1 100 Mb/s PMD Output Pair t and t F 100 Mb/s t and T2.8.2 100 Mb/s PMD Output Pair Transmit ...
Page 67
Receive Packet Latency Timing PMD Input Pair IDLE T2.9.1 CRS RXD[3:0] RX_DV RX_ER Parameter Description T2.9.1 Carrier Sense ON Delay T2.9.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first ...
Page 68
Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN Parameter Description T2.11.1 TX_CLK High/Low Time T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise Note: An attached Mac should drive the transmit signals ...
Page 69
Transmit Timing (Start of Packet) TX_CLK TX_EN TXD PMD Output Pair Parameter Description T2.13.1 Transmit Output Delay from the Falling Edge of TX_CLK Note: 1 bit time = 100 ns in 10Mb/s. 8.2.14 10BASE-T Transmit Timing (End of ...
Page 70
Receive Timing (Start of Packet TPRD T2.15.1 CRS RX_CLK T2.15.2 RX_DV 0000 RXD[3:0] Parameter Description T2.15.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.15.2 RX_DV Latency T2.15.3 Receive Data Latency Note: 10BASE-T RX_DV ...
Page 71
Mb/s Heartbeat Timing TX_EN TX_CLK COL Parameter Description T2.17.1 CD Heartbeat Delay T2.17.2 CD Heartbeat Duration 8.2.18 10 Mb/s Jabber Timing TXE PMD Output Pair COL Parameter Description T2.18.1 Jabber Activation Time T2.18.2 Jabber Deactivation Time T2.17.1 T2.17.2 ...
Page 72
Normal Link Pulse Timing Normal Link Pulse(s) Parameter Description T2.19.1 Pulse Width T2.19.2 Pulse Period Note: These specifications represent transmit timings. 8.2.20 Auto-Negotiation Fast Link Pulse (FLP) Timing T2.20.1 Fast Link Pulse(s) Parameter Description T2.20.1 Clock, Data Pulse ...
Page 73
Signal Detect Timing PMD Input Pair T2.21.1 SD+ internal Parameter Description T2.21.1 SD Internal Turn-on Time T2.21.2 SD Internal Turn-off Time Note: The signal amplitude on PMD Input Pair must be TP-PMD compliant. 8.2.22 100 Mb/s Internal Loopback ...
Page 74
Mb/s Internal Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T2.23.1 TX_EN to RX_DV Loopback Note: Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. www.national.com T2.23.1 Notes 10 Mb/s ...
Page 75
RMII Transmit Timing X1 TXD[1:0] TX_EN PMD Output Pair Parameter Description T2.24.1 X1 Clock Period T2.24.2 TXD[1:0], TX_EN, Data Setup to X1 rising T2.24.3 TXD[1:0], TX_EN, Data Hold from X1 rising T2.24.4 X1 Clock to PMD Output Pair Latency ...
Page 76
RMII Receive Timing IDLE (J/K) PMD Input Pair X1 T2.25.3 RX_DV CRS_DV RXD[1:0] RX_ER Parameter Description T2.25.1 X1 Clock Period T2.25.2 RXD[1:0], CRS_DV, RX_DV, and RX_ER output delay from X1 rising T2.25.3 CRS ON delay T2.25.4 CRS OFF delay ...
Page 77
Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) H/W or S/W Reset (with PHYAD = 00000) MODE Parameter Description T2.26.1 From software clear of bit 10 in the BMCR register to the transi- ...
Page 78
Mb TX_CLK Timing X1 TX_CLK Parameter Description T2.28 TX_CLK delay Note TX_CLK timing is provided to support devices that use X1 instead of TX_CLK as the reference for transmit Mll data. www.national.com ...
Page 79
Notes 79 www.national.com ...
Page 80
... National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other brand or product names may be trademarks or registered trademarks of their respective holders. ...
Page 81
... National Semiconductor Confidental Subject to change without notice. 81 REVISON 2.0 www.national.com ...