I2C-CPEV National Semiconductor, I2C-CPEV Datasheet
I2C-CPEV
Specifications of I2C-CPEV
Related parts for I2C-CPEV
I2C-CPEV Summary of contents
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... Quiet Design (low radiated emissions) COP8 ™ trademark of National Semiconductor Corporation. © 2004 National Semiconductor Corporation single-chip CMOS device is suited for applications requiring a full featured, in-system reprogrammable controller with large memory and low EMI. The same device is used for development, pre-production and volume production with a range of COP8 software and hardware development tools ...
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Block Diagram 4.0 Ordering Information COP8 CB Family and Feature Set Indicator CB = Low Brownout Voltage CC = High Brownout Voltage Brownout www.national.com Part Numbering Scheme Program Program Memory Memory No. Of ...
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General Description ..................................................................................................................................... 1 2.0 Features ....................................................................................................................................................... 1 3.0 Block Diagram .............................................................................................................................................. 2 4.0 Ordering Information .................................................................................................................................... 2 5.0 Connection Diagrams ................................................................................................................................... 6 6.0 Architectural Overview ................................................................................................................................. 8 6.1 EMI REDUCTION ...................................................................................................................................... 8 6.2 IN-SYSTEM PROGRAMMING AND VIRTUAL EEPROM ...
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TIMER T1 AND TIMER T2 .................................................................................................................... 35 12.2.1 Timer Operating Speeds .................................................................................................................. 35 12.2.2 Mode 1. Processor Independent PWM Mode ................................................................................. 35 12.2.3 Mode 2. External Event Counter Mode ........................................................................................... 36 12.2.4 Mode 3. Input Capture Mode .......................................................................................................... 36 ...
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INTRODUCTION ................................................................................................................................... 55 16.2 MASKABLE INTERRUPTS ................................................................................................................... 55 16.3 VIS INSTRUCTION ............................................................................................................................... 56 16.3.1 VIS Execution .................................................................................................................................. 57 16.4 NON-MASKABLE INTERRUPT ............................................................................................................ 58 16.4.1 Pending Flag .................................................................................................................................... 58 16.4.2 Software Trap .................................................................................................................................. 58 16.4.2.1 PROGRAMMING EXAMPLE: EXTERNAL INTERRUPT .......................................................... ...
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Connection Diagrams Top View Plastic Chip Package See NS Package Number V44A Top View LLP Package See NS Package Number LQA44A www.national.com 20022564 TSSOP Package See NS Package Number MTD48 20022555 6 20022559 Top View ...
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Port Type Alt. Function L0 I/O MIWU or Low Speed OSC In L1 I/O MIWU or CKX or Low Speed OSC Out L2 I/O MIWU or TDX L3 I/O MIWU or RDX L4 I/O MIWU or T2A L5 I/O MIWU ...
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Architectural Overview 6.1 EMI REDUCTION The COP8CBE9/CCE9 devices incorporate circuitry that guards against electromagnetic interference - an increasing problem in today’s microcontroller board designs. National’s patented EMI reduction technology offers low EMI clock circuitry, gradual turn-on output drivers (GTOs) ...
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Architectural Overview examples. In many cases, the instruction set can simulta- neously execute as many as three functions with the same single-byte instruction. JID: (Jump Indirect); Single byte instruction decodes exter- nal events and jumps to corresponding service routines ...
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... Absolute Maximum Ratings 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage at Any Pin Total Current into V Pin (Source) CC 8.0 Electrical Characteristics DC Electrical Characteristics (0˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. ...
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Electrical Characteristics DC Electrical Characteristics (0˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Output Current Levels B0-B3 Outputs Source (Weak Pull-Up Mode) Source (Push-Pull Mode) (Note 7) Sink (Push-Pull Mode) (Note ...
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AC Electrical Characteristics (0˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter MICROWIRE/PLUS Output Propagation Delay (t ) UPD Input Pulse Width Interrupt Input High Time Interrupt Input Low Time Timer 1 Input ...
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A/D Converter Electrical Characteristics (0˚C ≤ T mode only) (Continued) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Conversion Clock Period Conversion Time (including S/H Time) Operating Current Note 11: Resistance between ...
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DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Operating Voltage Power Supply Rise Time Power Supply Ripple (Note 2) Supply Current (Note 3) High Speed Mode CKI = 10 ...
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DC Electrical Characteristics (−40˚C ≤ T Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter RAM Retention Voltage, V (in HALT Mode) R Input Capacitance Voltage Force Execution from Boot ROM(Note 8) G6 ...
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A/D Converter Electrical Characteristics (−20˚C ≤ T (Single-ended mode only) Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. Parameter Resolution DNL INL Offset Error Gain Error Input Voltage Range Analog Input Leakage Current Analog Input Resistance ...
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Pin Descriptions The COP8CBE/CCE I/O structure enables designers to re- configure the microcontroller’s I/O functions with a single instruction. Each individual I/O pin can be independently configured as output pin low, output high, input with high impedance or input ...
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Pin Descriptions ration registers for G6 and G7 are used for special purpose functions as outlined below. Reading the G6 and G7 data bits will return zeros. The device will be placed in the HALT mode by writing a ...
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Pin Descriptions (Continued and RESET. For proper operation, no connection should be made on the device side of the emulator connec- tor. FIGURE 6. Emulation Connection 10.0 Functional Description The architecture of the device is ...
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Functional Description (Continued) 10.4 DATA MEMORY SEGMENT RAM EXTENSION Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S). The data store memory is either addressed directly by a single byte ...
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Functional Description (Continued) 10.4.1 Virtual EEPROM The Flash memory and the User ISP functions (see Section 5.7), provide the user with the capability to use the flash program memory to back up user defined sections of RAM. This effectively ...
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Functional Description (Continued) 10.7 RESET The device is initialized when the RESET pin is pulled low or the On-chip Brownout Reset is activated. FIGURE 8. Reset Logic The following occurs upon initialization: Port A: TRI-STATE (High Impedance Input) Port ...
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Functional Description (Continued) WATCHDOG (if enabled): The device comes out of reset with both the WATCHDOG logic and the Clock Monitor detector armed, with the WATCHDOG service window bits set and the Clock Moni- tor bit set. The WATCHDOG ...
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Functional Description One exception to the above is that the brownout circuit will insert a delay of approximately power up or any time the V drops below a voltage of about 1.8V. The device will CC ...
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Functional Description (Continued) FIGURE 11. Reset Circuit Using Power-On Reset 10.8 OSCILLATOR CIRCUITS The device has two crystal oscillators to facilitate low power operation while maintaining throughput when required. Fur- ther information on the use of the two oscillators ...
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Functional Description (Continued) 10.8.2 Clock Doubler This device contains a frequency doubler that doubles the frequency of the oscillator selected to operate the main microcontroller core. The details of how to select either the high speed oscillator or low ...
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Functional Description (Continued) 10.9.7 ENAD Register (Address X'00CB) ADCH3 ADCH2 ADCH1 ADCH0 ADMOD MUX Channel Select Mode Mux Out Prescale Select Bit 7 The ENAD register contains the following bits: ADCH3 ADC channel select bit ADCH2 ADC channel select ...
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In-System Programming (Continued) the page should be loaded. For mass erase operations, 0000 must be placed into the address registers. When read- ing the Option register, FFFF (hex) should be placed into the address registers. Registers ISPADHI and ISPADLO ...
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In-System Programming TABLE 8. PGMTIM Register Format (Continued R/W R/W R/W ...
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... Reset section. This assumes that the FLEX bit in the Option register was programmed to 1. 11.7 MICROWIRE/PLUS ISP National Semiconductor provides a program, which is avail- able from our web site at www.national.com/cop8, that is capable of programming a device from the parallel port of a PC. The software accepts manually input commands and is capable of downloading standard Intel HEX Format files ...
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In-System Programming TABLE 10. MICROWIRE/PLUS ISP Commands (Continued) Command Function BLOCKR Block Read WRITE_BYTE Write Byte BLOCKW Block Write EXIT EXIT INVALID N/A Note: The user must ensure that Block Writes do not cross a 64 byte boundary within ...
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In-System Programming Command/ Command Function Label Entry Point cpgerase Page Erase 0x17 cmserase Mass Erase 0x1A creadbf Read Byte 0x11 cblockr Block Read 0x26 cwritebf Write Byte 0x14 cblockw Block Write 0x23 exit EXIT 0x62 uwisp MICROWIRE/ 0x00 PLUS ...
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In-System Programming Register Name ISPADHI High byte of Flash Memory Address ISPADLO Low byte of Flash Memory Address ISPWR The user must store the byte to be written into this register before jumping into the write byte routine. ISPRD ...
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Timers The device contains a very versatile set of timers (T0, T1 and T2). Timers T1 and T2 and associated autoreload/capture registers power up containing random data. 12.1 TIMER T0 (IDLE TIMER) The device supports applications that require maintaining ...
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Timers (Continued) existing programs are updated to use this device, writing zero to these bits will cause the device to reset (see Section 13.0 Power Saving Features). RSVD: This bit is reserved and must be set to 0. ITSEL2:0: ...
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Timers (Continued) output and inverting the PWM duty cycle. If the PWM Timer is used in low speed mode or if the PWM output toggle is synchronous with the end of the instruction cycle, this prob- lem is not ...
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Timers (Continued) occurs in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt. Figure 18 ...
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Power Saving Features Today, the proliferation of battery-operated applications has placed new demands on designers to drive power consump- tion down. Battery operated systems are not the only type of applications demanding low power. The power budget con- straints ...
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Power Saving Features (Continued) high speed clock. When this bit = 1, then the Core clock will be the low speed clock. Before switching this bit to either state, the appropriate clock should be turned on and stabilized. DCEN ...
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Power Saving Features (Continued) underflows, the clock signals are enabled on the chip, allow- ing program execution to proceed. Thus, the delay is equal to 256 instruction cycles. Note: To ensure accurate operation upon start-up of the device using ...
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Power Saving Features (Continued) 13.4 DUAL CLOCK MODE OPERATION This mode of operation allows for high speed operation of the Core clock and low speed operation of the Idle Timer. This mode can be entered from either the High ...
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Power Saving Features (Continued) which was started as the part entered the IDLE mode is completed before the interrupt is serviced. This instruction should be a NOP which should follow the enter IDLE instruc- tion.) The user must reset ...
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Power Saving Features (Continued) amount of time seconds, and then automatically exits the IDLE mode and returns to normal program execution using the low speed clock. The device is placed in the IDLE mode under software ...
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Power Saving Features (Continued) 13.6 MULTI-INPUT WAKE-UP The Multi-Input Wake-up feature is used to return (wake-up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake-up/Interrupt feature may also be used to generate edge ...
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USART (Continued) 14.1 USART CONTROL AND STATUS REGISTERS The operation of the USART is programmed through three registers: ENU, ENUR and ENUI. 14.2 DESCRIPTION OF USART REGISTER BITS ENU — USART CONTROL AND STATUS REGISTER (Ad- dress at 0BA) ...
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USART (Continued) XBIT9/PSEL0: Programs the ninth bit for transmission when the USART is operating with nine data bits per frame. For seven or eight data bits per frame, this bit in conjunction with PSEL1 selects parity. Read/Write, cleared on ...
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USART (Continued) 14.4 USART OPERATION The USART has two modes of operation: asynchronous mode and synchronous mode. 14.4.1 Asynchronous Mode This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to ...
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USART (Continued) Stop bit selection bits in the control register. Note that an 14.6 USART INTERRUPTS The USART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt ...
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USART (Continued) where the USART clock is turned off for power saving pur- pose. The user must also turn the USART clock off when a different baud rate is chosen. The correspondences between the 5-bit Prescaler Select and Prescaler ...
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USART (Continued) Example: Asynchronous Mode: Crystal Frequency = 5 MHz Desired baud rate = 19200 Using the above equation can be calculated first 2)/(16 x 19200) = ...
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A/D Converter This device contains a 16-channel, multiplexed input, suc- cessive approximation, 10 bit Analog-to-Digital Converter. Pins AV and AGND are used for the voltage reference. CC 15.1 OPERATING MODES It supports both Single Ended and Differential modes of ...
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A/D Converter (Continued) TABLE 21. A/D Converter Channel Selection when the Multiplexor Output is Enabled Select Bits ADCH3 ADCH2 ADCH1 ...
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A/D Converter (Continued) FIGURE 26. A/D with Single Ended Mux Output Feature Enabled FIGURE 27. A/D with Differential Mux Output Feature Enabled 15.1.1.3 MODE SELECT This 1-bit field is used to select the mode of operation (single ended or ...
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A/D Converter (Continued) 15.2 A/D OPERATION The A/D conversion is completed within fifteen A/D converter clocks. The A/D Converter interface works as follows. Setting the ADBSY bit in the A/D control register ENAD initiates an A/D conversion. The conversion ...
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Interrupts 16.1 INTRODUCTION The device supports eleven vectored interrupts. Interrupt sources include Timer 1, Timer 2, Timer T0, Port L Wake-up, Software Trap, MICROWIRE/PLUS, USART and External Input. All interrupts force a branch to location 00FF Hex in program ...
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Interrupts (Continued) An interrupt is an asychronous event which may occur be- fore, during, or after an instruction cycle. Any interrupt which occurs during the execution of an instruction is not acknowl- edged until the start of the next ...
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Interrupts (Continued) The default VIS interrupt vector can be useful for applica- tions in which time critical interrupts can occur during the servicing of another interrupt. Rather than restoring the pro- gram context ( etc.) and executing ...
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Interrupts (Continued) 16.4 NON-MASKABLE INTERRUPT 16.4.1 Pending Flag There is a pending flag bit associated with the non-maskable Software Trap interrupt, called STPND. This pending flag is not memory-mapped and cannot be accessed directly by the software. The pending ...
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Interrupts (Continued) user program should contain the Software Trap routine to perform a recovery procedure rather than a return to normal execution. Under normal conditions, the STPND flag is reset by a RPND instruction in the Software Trap service ...
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Interrupts (Continued SERVICE: RBIT,EXPND,PSW . . . RET I 16.5 PORT L INTERRUPTS Port L provides the user with an additional eight fully select- able, edge sensitive interrupts which are all vectored into the same service ...
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WATCHDOG/Clock Monitor TABLE 28. WATCHDOG Service Window Select WDSVR WDSVR Monitor Bit 7 Bit 17.1 CLOCK MONITOR The Clock Monitor aboard the device can be selected ...
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WATCHDOG/Clock Monitor (Continued) 17.3 WATCHDOG AND CLOCK MONITOR SUMMARY The following salient points regarding the WATCHDOG and CLOCK MONITOR should be noted: • Both the WATCHDOG and CLOCK MONITOR detector circuits are inhibited during RESET. • Following RESET, the ...
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MICROWIRE/PLUS TABLE 30. MICROWIRE/PLUS Master Mode Clock Select SL1 SL0 Where t is the instruction cycle clock C 18.1 MICROWIRE/PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE/PLUS to ...
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MICROWIRE/PLUS 18.1.2.1 ALTERNATE SK PHASE OPERATION AND SK IDLE POLARITY The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the ...
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MICROWIRE/PLUS FIGURE 35. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being High FIGURE 36. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being High 19.0 Memory Map All RAM, ports and registers ...
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Memory Map (Continued) Address Contents S/ADD REG xxC5 Timer T2 Autoload Register T2RB Upper Byte xxC6 Timer T2 Control Register xxC7 WATCHDOG Service Register (Reg:WDSVR) xxC8 MIWU Edge Select Register (Reg:WKEDG) xxC9 MIWU Enable Register (Reg:WKEN) xxCA MIWU Pending ...
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Instruction Set (Continued) point to the desired memory location. In the immediate mode, the data byte to be used is contained in the instruction itself. Each addressing mode has its own advantages and disad- vantages with respect to flexibility, ...
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Instruction Set (Continued) Different addressing modes are used to specify the new address for the Program Counter. The choice of addressing mode depends primarily on the distance of the jump. Farther jumps sometimes require more instruction bytes in order ...
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Instruction Set (Continued) 20.4.3 Load and Exchange Instructions The load and exchange instructions write byte values in registers or memory. The addressing mode determines the source of the data. Load (LD) Load Accumulator Indirect (LAID) Exchange (X) 20.4.4 Logical ...
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Instruction Set (Continued) 20.6 INSTRUCTION SET SUMMARY ADD A,Meml ADD ADC A,Meml ADD with Carry SUBC A,Meml Subtract with Carry AND A,Meml Logical AND ANDSZ A,Imm Logical AND Immed., Skip if Zero OR A,Meml Logical OR XOR A,Meml Logical ...
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Instruction Set (Continued) JSRL Addr. Jump SubRoutine Long JSR Addr. Jump SubRoutine JSRB Addr Jump SubRoutine Boot ROM JID Jump InDirect RET RETurn from subroutine RETSK RETurn and SKip RETI RETurn from Interrupt INTR Generate an Interrupt NOP No ...
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Instruction Set (Continued) Register [ (Note 23) 1 (Note 23) 1/1 LD B,Imm LD B,Imm LD Mem,Imm 2/2 LD Reg,Imm IFEQ MD,Imm > Note 23: = Memory location addressed directly. ...
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Nibble Lower 73 www.national.com ...
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Development Support 21.1 TOOLS ORDERING NUMBERS FOR THE COP8 FLASH FAMILY DEVICES This section provides specific tools ordering information for the devices in this datasheet, followed by a summary of the tools and development kits available at print time. ...
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Development Support Hardware COP8-EMFlash-00 Emulators COP8-DMFlash-00 COP8-IMFlash-00 Emulator Null COP8-EMFA-68N Target COP8-EMFA-28N Emulator Target COP8-EMFA-44P Package Adapters COP8-EMFA-68P NiceMon Debug COP8-SW-NMON Monitor Utility Development and Production Programming Tools Programming COP8-PGMA-28DF1 Adapters COP8-PGMA-28SF1 (For any COP8-PGMA-44PF1 programmer COP8-PGMA-44CSF supporting flash ...
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Development Support 21.2 COP8 TOOLS OVERVIEW COP8 Evaluation Software and Reference Designs - Software and Hardware for: Evaluation of COP8 Development Environments; Learning about COP8 Architecture and Features; Demonstrating Application Specific Capabilities. Product WCOP8 IDE and Software Evaluation downloads ...
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Development Support Hardware Tools for: Real-time Emulation; Target Hardware Debug; Target Design Test. Product COP8Flash COP8 In-Circuit Emulator for Flash Families. Windows based development and Emulators - real-time in-circuit emulation tool, with trace (EM=None; DM/IM=32k), s/w COP8-EMFlash breakpoints (DM=16, ...
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Development Support Vendor Home Office Embedded Results P.O. Box 200 LTD. Aberystwyth, SY23 2WD, UK Tel/Fax: +44 (0)8707 446 807 K and K Kaergaardsvej 42 DK-8355 Development ApS Solbjerg Denmark Fax: +45-8692-8500 National 2900 Semiconductor Dr. Semiconductor Santa Clara, ...
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Physical Dimensions Order Number COP8CBE9HLQ9 or COP8CCE9HLQ9 Order Number COP8CBE9IMT9 or COP8CCE9IMT9 inches (millimeters) unless otherwise noted LLP Package (LQA) COP8CCE9HLQ7 NS Package Number LQA44A TSSOP Package (MTD) COP8CCE9IMT7 NS Package Number MTD48 79 www.national.com ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...