I2C-CPEV National Semiconductor, I2C-CPEV Datasheet - Page 37

• Manufacturer Part Number: I2C-CPEV
• Description: BOARD INTERFACE USB I2C
• Manufacturer: National Semiconductor

Specifications of I2C-CPEV

• Main Purpose: Interface, USB to I²C
• Utilized Ic / Part: COP8CBE9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

Mode
12.0 Timers
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 18 shows a block diagram of the timer T1 in Input
Capture mode. T2 is identical to T1.
12.3 TIMER CONTROL FLAGS
The control bits and their functions are summarized below.
1
2
3
TxC3
FIGURE 18. Timer in Input Capture Mode
TxC3
Timer mode control
1
1
0
0
0
1
0
1
(Continued)
TxC2
0
0
0
0
1
1
1
1
TxC1
1
0
0
1
0
0
1
1
PWM: TxA Toggle
PWM: No TxA Toggle
External Event Counter
External Event Counter
Captures:
TxA Pos. Edge
TxB Pos. Edge
Captures:
TxA Pos. Edge
TxB Neg. Edge
Captures:
TxA Neg. Edge
TxB Pos. Edge
Captures:
TxA Neg. Edge
TxB Neg. Edge
TABLE 15. Timer Operating Modes
20022521
Description
37
The timer mode control bits (TxC3, TxC2 and TxC1) are
detailed in Table 15, Timer Operating Modes.
When the high speed timers are counting in high speed
mode, directly altering the contents of the timer upper or
lower registers, the PWM outputs or the reload registers is
not recommended. Bit operations can be particularly prob-
lematic. Since any of these six registers or the PWM outputs
can change as many as ten times in a single instruction
cycle, performing an SBIT or RBIT operation with the timer
running can produce unpredictable results. The recom-
mended procedure is to stop the timer, perform any changes
to the timer, the PWM outputs or reload register values, and
then re-start the timer. This warning does not apply to the
timer control register. Any type of read/write operation, in-
cluding SBIT and RBIT may be performed on this register in
any operating mode.
TxC2
TxC1
TxC0
TxPNDA Timer Interrupt Pending Flag
TxENA
TxPNDB Timer Interrupt Pending Flag
TxENB
Autoreload RA
Autoreload RA
Timer
Underflow
Timer
Underflow
Pos. TxA Edge
or Timer
Underflow
Pos. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Neg. TxA
Edge or Timer
Underflow
Interrupt A
Source
Timer mode control
Timer mode control
Timer Start/Stop control in Modes 1 and 2 (Pro-
cessor Independent PWM and External Event
Counter), where 1 = Start, 0 = Stop
Timer Underflow Interrupt Pending Flag in Mode
3 (Input Capture)
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Timer Interrupt Enable Flag
1 = Timer Interrupt Enabled
0 = Timer Interrupt Disabled
Autoreload RB
Autoreload RB
Pos. TxB Edge
Pos. TxB Edge
Pos. TxB Edge
Neg. TxB
Edge
Pos. TxB
Edge
Neg. TxB
Edge
Interrupt B
Source
t
t
TxA Pos. Edge
TxA Neg. Edge
t
t
t
t
Timer Counts
C
C
C
C
C
C
or MCLK
or MCLK
or MCLK
or MCLK
or MCLK
or MCLK
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