ISL54220IRUEVAL1Z Intersil, ISL54220IRUEVAL1Z Datasheet - Page 16

• Manufacturer Part Number: ISL54220IRUEVAL1Z
• Description: EVALUATION BOARD FOR ISL54220
• Manufacturer: Intersil

Specifications of ISL54220IRUEVAL1Z

• Main Purpose: Interface, 2:1 Multiplexer
• Embedded: No
• Utilized Ic / Part: ISL54220
• Primary Attributes: 2 x SPDT Analog Switch
• Secondary Attributes: 2.7 V ~ 5.5 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Package Outline Drawing
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 4, 9/09
INDEX AREA
2X
2X
1.80
6
TYPICAL RECOMMENDED LAND PATTERN
0.10 C
1.00
0.10 C
0.50
0.20
10
LAND PATTERN
TOP VIEW
16
2.20
1.00
0.60
0.40
1
1.80
2
0.20
0.40
A
B
0.127 REF
ISL54220
NX (0.20)
5
NOTES:
SEATING PLANE
PIN #1 ID
10.
(DATUM A)
SECTION "C-C"
0.50
1.
2.
3.
4.
5.
6.
7.
8.
9.
0.05 C
Dimensioning and tolerancing conform to ASME Y14.5-1994.
N is the number of terminals. Total 10 leads.
Nd and Ne refer to the number of terminals on D (4) and E (6) side,
respectively.
All dimensions are in millimeters. Tolerances ±0.05mm unless
otherwise noted. Angles are in degrees.
Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Maximum package warpage is 0.05mm.
Maximum allowable burrs is 0.076mm in all directions.
JEDEC Reference MO-255.
For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
0.10 C
(0.05 MAX)
0.40 BSC
1
7
BOTTOM VIEW
0.5
0.05 MAX
SIDE VIEW
DETAIL "X"
2
NX 0.40
5
C C
NX 0.20
10X
(DATUM B)
e
0.40 BSC
0.10 M C A B
0.05 M C
C
L
5
C
TERMINAL TIP
0.40
0.40
February 4, 2010
FN6819.1