ISL54059EVAL1Z Intersil, ISL54059EVAL1Z Datasheet - Page 14
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ISL54059EVAL1Z
Manufacturer Part Number
ISL54059EVAL1Z
Description
EVALUATION BOARD FOR ISL54059
Manufacturer
Intersil
Specifications of ISL54059EVAL1Z
Main Purpose
Interface, 2:1 Multiplexer
Embedded
No
Utilized Ic / Part
ISL54059
Primary Attributes
2 x SPDT Analog Switch
Secondary Attributes
1.8 V ~ 6.5 V Supply
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
NX (b)
5
SECTION "C-C"
SEATING PLANE
INDEX AREA
0.05 C
0.10 C
2X
2X
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
6
1.80
0.10 C
PIN #1 ID
(A1)
(DATUM A)
1.00
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
A
0.10 C
L1
0.50
0.20
A1
For information regarding Intersil Corporation and its products, see www.intersil.com
10
N
BOTTOM VIEW
LAND PATTERN
SIDE VIEW
C C
TOP VIEW
14
1
1
7
2.20
1.00
0.60
0.40
D
e
e
2
2
C L
NX L
5
0.20
NX b
10X
A
0.40
(DATUM B)
C
TERMINAL TIP
0.10 M C A B
0.05 M C
B
E
5
L
ISL54059
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
NOTES:
10. For additional information, to assist with the PCB Land Pattern
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
SYMBOL
respectively.
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
Design effort, see Intersil Technical Brief TB389.
A1
A3
Nd
Ne
L1
A
D
E
N
b
e
L
θ
0.45
0.15
1.75
1.35
0.35
0.45
MIN
0
-
MILLIMETERS
0.127 REF
NOMINAL
0.40 BSC
0.50
0.20
1.80
1.40
0.40
0.50
10
2
3
-
-
0.55
0.05
0.25
1.85
1.45
0.45
0.55
MAX
12
Rev. 3 6/06
March 11, 2011
NOTES
FN6579.2
5
2
3
3
4
-
-
-
-
-
-
-
-