LMX25121065EVAL/NOPB National Semiconductor, LMX25121065EVAL/NOPB Datasheet - Page 9
![EVALUATION BOARD FOR LMX25121065](/photos/9/9/90991/lmx25121065eval_sml.jpg)
LMX25121065EVAL/NOPB
Manufacturer Part Number
LMX25121065EVAL/NOPB
Description
EVALUATION BOARD FOR LMX25121065
Manufacturer
National Semiconductor
Series
PLLatinum™r
Datasheets
1.LMX2512LQ0967NOPB.pdf
(18 pages)
2.LMX2430EVAL.pdf
(8 pages)
3.LMX25121065EVALNOPB.pdf
(24 pages)
Specifications of LMX25121065EVAL/NOPB
Main Purpose
Timing, Frequency Synthesizer
Embedded
No
Utilized Ic / Part
LMX2512
Primary Attributes
Single Fractional-N and Integer-N PLL with VCO
Secondary Attributes
1.065GHz, CodeLoader Graphical User Interface
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*LMX25121065EVAL
*LMX25121065EVAL/NOPB
LMX25121065EVAL
*LMX25121065EVAL/NOPB
LMX25121065EVAL
Functional Description
MICROWIRE INTERFACE
The programmable register set is accessed via the
MICROWIRE serial interface. The interface comprises three
signal pins: CLK, DATA, and LE (Latch Enable). Serial data
(DATA) is clocked into the 24-bit shift register on the rising
(Continued)
FIGURE 2. Lock Detect Flow Diagram
9
edge of the clock (CLK). The last bits decode the internal
control register address. When the latch enable (LE) transi-
tions from LOW to HIGH, data stored in the shift registers is
loaded into the corresponding control register.
20068006
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