FPDXSDUR-43USB/NOPB National Semiconductor, FPDXSDUR-43USB/NOPB Datasheet
FPDXSDUR-43USB/NOPB
Specifications of FPDXSDUR-43USB/NOPB
Related parts for FPDXSDUR-43USB/NOPB
FPDXSDUR-43USB/NOPB Summary of contents
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... FPD to Serdes (UR) Translator Chip User’s Manual NSID: FPDXSDUR-43USB DS99R421 Evaluation Kit Rev 0.0 National Semiconductor Corporation Date: 5/12/2008 Page ...
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... SERIALIZER (TX) PCB LAYOUT: ...................................................................................................................... 32 SERIALIZER (TX) PCB STACKUP: .................................................................................................................... 35 DESERIALIZER (RX) PCB LAYOUT:................................................................................................................. 36 DESERIALIZER (RX) PCB STACKUP:............................................................................................................... 39 Table of Contents S B ......................................................................................... 8 ERIALIZER OARD O FPD IDC C UTPUT INK INOUT BY PCB: ................................................................................................... ................................................................................. 14 E SERIALIZER OARD ...................................................................................... 15 E SERIALIZER OARD LVCMOS IDC C BY ONNECTOR PCB: ................................................................................................ 18 SERIALIZER National Semiconductor Corporation ........................................... 11 ONNECTOR .................................................................... 17 Date: 5/12/2008 Page ...
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... Introduction: National Semiconductor’s DS99R421 standard multi-channel LVDS to FPD-Link II translator SERDES evaluation kit contains 1 - DS99R421 translator board and 1 - DS90UR124 De-serializer (Rx) board, and 1 - two (2) meter high speed USB 2.0 cable. Note: the evaluation boards are not for EMI testing. The evaluation boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals, additional pads for termination, loading, and multiple connector options ...
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... One 2-meter high speed USB 2.0 cable (4-pin USB A to 5-pin mini USB) 4) Evaluation Kit Documentation (this manual) 5) DS99R421 and DS90UR241/124 Datasheet SERDES Typical Application: Figure 1a. Typical Application (18-bit RGB Color) Figure 1b. Typical SERDES System Diagram National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Figures 1a and 1b illustrate the use of the chipset (DS99R421/DS90UR124 Host to Flat Panel Interface. The chipsets support up to 18-bit color depth TFT LCD Panels. Refer to the proper datasheet information on chipset provided on each board for more detailed information. National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Note +4V is the absolute MAXIMUM voltage (not operating voltage) that should ever be applied to the translator (DS99R421) or de-serializer (DS90UR124) VDD terminal. Damage to the device(s) can result if the voltage maximum is exceeded side of cable harness to the DS99R421 board and National Semiconductor Corporation 4 MIN to the DS90UR124 de- See text on Date: 5/12/2008 Page ...
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... J4, J5 Note: VDD and VSS MUST be applied externally from here. J1 JP7 S1 NOT FOR EMI TESTING The 100 ohm terminations are NOT FOR EMI TESTING National Semiconductor Corporation R5 VR1, JP6 Note: Connect cable BACKSIDE. P2 (BACKSIDE) P1 (TOPSIDE) (UNSTUFFED) FPD-Link II OUTPUT LVDS INPUTS LVCMOS INPUTS ...
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... Input = L Input = H Powered Normal Down operation (Default) Disabled Enabled (Default) ≈350mV ≈700mV (Default) BIST BIST DISABLED ENABLED. MUST be Note: low for DS90UR124 normal BISTEN MUST operation also be set High. (see (Default) datasheet for operational modes) National Semiconductor Corporation S1 Date: 5/12/2008 Page ...
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... AFTER the cable/connector. OPEN (floating) Disabled – no jumper (Default) Clockwise ( R6) = increases R value PRE which decreases pre 40, emphasis Ω value is based Ω National Semiconductor Corporation CLOSED (Path to GND) Enabled – With jumper Counter- Clockwise decreases R value PRE which increases pre- emphasis Date: 5/12/2008 Page ...
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... BLACK WIRE A USB VDD Red wire tied to VDD Black wire tied to VDD P2 National Semiconductor Corporation VSS OPEN Red wire Red wire tied to VSS floating (Default) (not recommended) Black wire Black wire tied to VSS floating (Default) (not recommended) ...
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... RxCLKIN- 15 RxCLKIN+ 16 VSS 17 VSS VSS OS INPUT (3.3v_LVCMOS) JP3 pin no. Symbol 1 OS1 2 VSS 3 OS2 4 VSS 5 OS3 6 VSS FPD-Link II OUTPUT P3 pin no. Symbol 1 RED 2 DOUT+ 3 DOUT- 4 BLK National Semiconductor Corporation P1 (topside) (not mounted) FPD-Link II OUTPUT pin no. name 5 JP2 DOUT- 2 DOUT+ 1 JP1 Date: 5/12/2008 Page ...
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... Header 2X3-Pin Header 2X10-Pin Header, open 2mm_2X5 BANANA mini USB 5pin_open USB A 100 ohm,0402 5.76K 0 Ohm,0402 10K SW DIP-4 DS99R421 SVR20K TP_0402 National Semiconductor Corporation PCB Footprint CAP/HDC-0402 CAP/N 3528-21_EIA CAP/HDC-1206 CAP/EIA-B 3528-21 CAP/HDC-0603 CAP/HDC-0603 Header/3P Header/2P Header/2X3P Header/2X10P CON/HDR-10P-B CON/BANANA-S ...
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... Rising or falling edge reference clock is also selected by S1: HIGH (rising) or LOW (falling). The 50 pin IDC Connector J3 provides access to the 24 bit LVCMOS and clock outputs. J4, J5 Note: Vcc and Gnd MUST be applied externally here (BACKSIDE) (UNSTUFFED) S2 JP3 National Semiconductor Corporation JP4 J3 FPD-Link II INPUTS LVCMOS OUTPUTS FUNCTION CONTROLS POWER SUPPLY Date: 5/12/2008 Page ...
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... Disabled (Default) Per Channel pass/fail; RxOUT[23:0] =H: pass; RxOUT[23:0] =H: fail Randomizer ON. (Default) Note: DS99R421 RAOFF MUST also be set Low. (Default) National Semiconductor Corporation Input = H S1 Normal Operational (Default) Disabled Don’t care Input = H S2 Rising Edge Enabled (Default) BIST Mode Enabled RxOUT[7:0]: ...
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... JUMPER IN JP3. JP4: PASS Monitor Reference Description PASS Receiver BIST monitor PASS flag Note: DO NOT PUT A SHORTING JUMPER IN JP1. Output = L unlocked Output = L FAIL National Semiconductor Corporation Output = H JP3 PLL LOCKED (LED2 will illuminate) Output = H JP4 PASS (LED1 will illuminate) Date: 5/12/2008 Page ...
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... DS90UR241 Tx. To view the serial stream correctly, do not trigger on the probe monitoring the serial stream. VDD Red wire tied to VDD Black wire tied to VDD RED WIRE + _ BLACK WIRE National Semiconductor Corporation VSS OPEN Red wire Red wire tied to VSS floating (Default) (not recommended) Black wire ...
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... ROUT10 23 ROUT11 25 ROUT12 27 ROUT13 29 ROUT14 31 ROUT15 33 ROUT16 35 ROUT17 37 ROUT18 39 ROUT19 41 ROUT20 43 ROUT21 45 ROUT22 47 ROUT23 49 TCLK all even pins VSS TTL OUTPUT JP3 pin no. Symbol 1 LOCK (PLL) 2 VSS TTL OUTPUT JP4 pin no. Symbol 1 PASS (BIST) 2 VSS National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Header 2-Pin Header_open mini USB 5pin_open Hirose GT17H-4P-2H IDC2X25_Unshrouded BANANA 0402_orange_LED 0603_green_LED 100 ohm,0402 10K SW DIP-3 SW DIP-6 DS90UR124 National Semiconductor Corporation PCB Footprint CAP/HDC-0402 CAP/HDC-0402 3528-21_EIA CAP/N CAP/HDC-1206 CAP/EIA-B 3528-21 CAP/HDC-0603 CAP/HDC-0603 Header/3P Header/2P mini_USB_surface_mount Hirose GT17H-4P-2H IDC-50 ...
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... The following is a list of typical test equipment that may be used to monitor the output signals from the RX: 1) LCD Display Panel which supports digital RGB (3.3V_LVCMOS) inputs. 2) National Semiconductor DS99R421 LVDS to FPD-Link II translator 3) Optional – Logic Analyzer or Oscilloscope 4) Any SCOPE with a bandwidth of at least 43MHz for TTL and/or 2GHz for looking at the differential signal ...
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... The picture below shows a typical test set up using a Graphics Controller and LCD Panel. Figure 2. Typical SERDES Setup of LCD Panel Application The picture below shows a typical test set up using a generator and scope. Figure 3. Typical SERDES Test Setup for Evaluation National Semiconductor Corporation Date: 5/12/2008 Page ...
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... VDDs can be combined into four (4) groupings as shown (top to bottom): 1-Analog-LVDS, 2-Digital, 3-Analog-FPD-Link II, and 4-Analog-PLL/VCO for best performance. Absolute minimum grouping should be Analog Power and Digital Power. Decoupling specified (C1-C8) is the minimum that should be used. Figure 6. Typical DS90C241 Tx SERDES Hookup National Semiconductor Corporation Date: 5/12/2008 Page ...
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... ROUT0 ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 ROUT6 ROUT7 RIN+ ROUT8 ROUT9 ROUT10 RIN- ROUT11 ROUT12 ROUT13 ROUT14 RPWDNB ROUT15 REN ROUT16 RRFB ROUT17 ROUT18 ROUT19 ROUT20 ROUT21 ROUT22 ROUT23 RESRVD RCLK LOCK National Semiconductor Corporation 3. LVCMOS Parallel Interface Date: 5/12/2008 Page ...
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... DEN on the Serializer board and REN on the Deserializer board is set HIGH. Check for shorts in the cables connecting the Translator and RX boards. Use a larger power supply that will provide enough current for the demo boards, a 500mA minimum power supply is recommended. National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Digital Video Pattern Generator – Astro Systems VG-835 (or equivalent): Extra Component References TDK Corporation of America 1740 Technology Drive, Suite 510 San Jose, CA 95110 Phone: (408) 437-9585, Fax: (408) 437-9591 www.component.tdk.com Optional EMI Filters – TDK Chip Beads (or equivalent) National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Serializer (Tx) PCB Schematic: Appendix National Semiconductor Corporation Date: 5/12/2008 Page ...
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... National Semiconductor Corporation Date: 5/12/2008 Page ...
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... National Semiconductor Corporation Date: 5/12/2008 Page ...
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... De-serializer (Rx) PCB Schematic: National Semiconductor Corporation Date: 5/12/2008 Page ...
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... National Semiconductor Corporation Date: 5/12/2008 Page ...
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... National Semiconductor Corporation Date: 5/12/2008 Page ...
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... National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Serializer (Tx) PCB Layout: TOP VIEW National Semiconductor Corporation BOTTOMSIDE VIEW Date: 5/12/2008 Page ...
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... PRIMARY COMPONENT SIDE – LAYER 1 SECONDARY COMP SIDE – LAYER 4 PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) National Semiconductor Corporation GROUND PLANE (VSS) – LAYER 2 SECONDARY COMP SIDE – SOLDER MASK (LAYER 4) POWER PLANE (VDD) – LAYER 3 Date: 5/12/2008 Page ...
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... PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4) National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Serializer (Tx) PCB Stackup: National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Deserializer (Rx) PCB Layout: TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date: 5/12/2008 Page ...
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... PRIMARY COMPONENT SIDE – LAYER 1 SECONDARY COMP SIDE – LAYER 4 PRIMARY COMP SIDE – SOLDER MASK (LAYER 1) National Semiconductor Corporation GROUND PLANE (VSS) – LAYER 2 SECONDARY COMP SIDE – SOLDER MASK (LAYER 4) POWER PLANE (VDD) – LAYER 3 Date: 5/12/2008 Page ...
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... PRIMARY COMP SIDE – SOLDER PASTE (LAYER 1) PRIMARY COMP SIDE – SILKSCREEN (LAYER 1) SECONDARY COMP SIDE – SOLDER PASTE (LAYER 4) SILKSCREEN COMP SIDE – SILKSCREEN (LAYER 4) National Semiconductor Corporation Date: 5/12/2008 Page ...
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... Deserializer (Rx) PCB Stackup: National Semiconductor Corporation Date: 5/12/2008 Page ...