FPDXSDUR-43USB/NOPB National Semiconductor, FPDXSDUR-43USB/NOPB Datasheet - Page 9

• Manufacturer Part Number: FPDXSDUR-43USB/NOPB
• Description: KIT EVAL DS99R421 CONV TO LVDS
• Manufacturer: National Semiconductor

Specifications of FPDXSDUR-43USB/NOPB

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: DS90UR124, DS99R421
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Other names: FPDXSDUR-43USB

FPD-LINK LVDS RECEIVER INPUT PINS
28, 30, 32
29, 31, 33
34
35
OVER SAMPLED INPUT PINS
3-1
CONTROL AND CONFIGURATION PINS
4
15
10
18
36, 24, 21, 9
BIST MODE PINS
27
LVDS SERIALIZER OUTPUT PINS
14
13
POWER / GROUND PINS
5
6
Pin Descriptions
Pin #
RxIN[2:0]−
RxIN[2:0]+
RxCLKIN−
RxCLKIN+
OS[2:0]
PWDNB
DEN
PRE
VODSEL
RESRVD
BISTEN
DOUT+
DOUT−
V
V
DD
SS
Pin Name
P1
P1
LVDS_I
LVDS_I
LVDS_I
LVDS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I/O Reserved. This pin MUST be tied LOW.
LVCMOS_I
LVDS_O
LVDS_O
V
GND
DD
I/O/PWR
LVDS Receiver inverted Data Inputs (−)
LVDS Receiver true Data Inputs (+)
LVDS Receiver inverted reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
LVDS Receiver true reference Clock Inputs.
Used to strobe data at the RxIN inputs and to drive the receiver PLL
Over Sampled Receiver Data Inputs with Schmitt trigger
Power Down Bar
PWDNB = H; Device is Enabled and ON
PWDNB = L; Device is in power down mode (Sleep), LVDS Driver D
are in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Serializer LVDS Driver D
Outputs are in TRI-STATE, PLL still operational and locked to TCLK.
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R
Resistor value determines pre-emphasis level. Recommended value R
I
See Applications Information section for more details.
VOD Level Select
VODSEL = L; LVDS Driver Output is ±500 mV (R
VODSEL = H; LVDS Driver Output is ±900 mV (R
For normal applications, set this pin LOW. For long cable applications where a larger
VOD is required, set this pin HIGH.
See Applications Information section for more details.
Control Pin for BIST Mode Enable (ACTIVE H)
BISTEN = L; Default at Low, Normal Mode
BISTEN = H; BIST mode active
Note: Sequence order for proper function of BIST mode:
1) DS99R421 BISTEN = H.
2) DS99R421 PLL must be locked (10 ms).
3) DS90UR124 PLL must be locked.
4) Select BISTM error reporting mode on DS90UR124.
5) DS90UR124 switch BISTEN from L to H.
Serializer LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D
should be AC Coupled to this pin with a 100 nF capacitor.
Serializer LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D
should be AC Coupled to this pin with a 100 nF capacitor.
Analog Power supply, PLL POWER
Analog Ground, PLL GROUND
max
= [48 / R
PRE
], R
9
PREmin
= 6 kΩ
Description
T
T
= 100Ω)
= 100Ω)
OUT+
OUT-
pin. The interconnect
pin. The interconnect
OUT
PRE
www.national.com
(+/-) Outputs
≥
PRE
6 kΩ;
OUT
.
(+/-)