DS2148DK Maxim Integrated Products, DS2148DK Datasheet - Page 13

• Manufacturer Part Number: DS2148DK
• Description: KIT DESIGN LIU DS2148 3/5V T1/E1
• Manufacturer: Maxim Integrated Products

Specifications of DS2148DK

• Main Purpose: Telecom, Line Interface Units (LIUs)
• Utilized Ic / Part: DS2148
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

RTIP/RRING
TTIP/TRING
NAME
RNEG
TNEG
TCLK
(R/W)
RPOS
TPOS
TEST
VSM
V
WR
V
DD
SS
27/28
34/37
21/36
22/35
PIN
39
38
43
26
42
41
20
3
I/O
O
O
O
I
I
I
I
I
-
I
-
I
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section
for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section
for details.
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These
pins connect via a 1:1 transformer to the line. See Section
Transmit Clock. A 2.048MHz or 1.544MHz primary clock. Used to clock
data through the transmit side formatter. Can be sourced internally by
MCLK or RCLK. See Common Control Register 1 and
Tri-state Control. Set high to tri-state all outputs and I/O pins (including
the parallel control port). Set low for normal operation. Useful in board
level testing.
Transmit Negative Data. Sampled on the falling edge (CCR2.1 = 0) or
the rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto
the line.
Transmit Positive Data. Sampled on the falling edge (CCR2.1 = 0) or the
rising edge (CCR2.1 = 1) of TCLK for data to be transmitted out onto the
line.
Transmit Tip and Ring. Analog line driver outputs. These pins connect
via a step-up transformer to the line. See Section
5.0V ±5% Positive Supply
Voltage Supply Mode. Should be tied high for 5V operation
Signal Ground
Active-Low Write Input (Read/Write). See the bus timing diagrams in
Section 10.
13 of 73
FUNCTION
5
for details.
Figure
5
for details.
1-3.
6.4
6.2