DS2148DK Maxim Integrated Products, DS2148DK Datasheet - Page 15

• Manufacturer Part Number: DS2148DK
• Description: KIT DESIGN LIU DS2148 3/5V T1/E1
• Manufacturer: Maxim Integrated Products

Specifications of DS2148DK

• Main Purpose: Telecom, Line Interface Units (LIUs)
• Utilized Ic / Part: DS2148
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 2-5. Pin Descriptions in Serial Port Mode (Sorted by Pin Name,
DS2148T)
RTIP/RRING
RCL/LOTC
BIS0/BIS1
BPCLK
NAME
MCLK
RCLK
RNEG
HRST
OCES
PBEO
SCLK
RPOS
ICES
INT
NA
CS
32/33
27/28
PIN
31
29
23
30
24
40
25
39
38
1
8
9
5
-
I/O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Bus Interface Select Bits 0 & 1. Used to select bus interface option. See
Table 2-1
Backplane Clock. A 16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz
clock output that is referenced to RCLK selectable via CCR5.7 and
CCR5.6. In hardware mode, defaults to 16.384MHz output.
Active-Low Chip Select. Must be low to read or write to the device.
Hardware Reset. Bringing HRST low will reset the DS2148 setting all
control bits to their default state of all zeros.
Input Clock Edge Select. Selects whether the serial port data input (SDI)
is sampled on rising (ICES =0) or falling edge (ICES = 1) of SCLK.
Active-Low Interrupt. Flags host controller during conditions and change
of conditions defined in the Status Register. Active low, open drain output.
Master Clock. A 2.048MHz (±50ppm) clock source with TTL levels is
applied at this pin. This clock is used internally for both clock/data
recovery and for jitter attenuation. Use of a T1 1.544MHz clock source is
optional. See Note 1 on clock accuracy at the end of this table.
Not Assigned. Should be tied low.
Output Clock Edge Select. Selects whether the serial port data output
(SDO) is valid on the rising (OCES = 1) or falling edge (OCES = 0) of
SCLK.
PRBS Bit Error Output. The receiver will constantly search for a 2
or a 2
high if out of synchronization with the PRBS pattern. Goes low when
synchronized to the PRBS pattern. Any errors in the received pattern after
synchronization will cause a positive going pulse (with same period as E1
or T1 clock) synchronous with RCLK. PRBS bit errors can also be
reported to the ECR1 and ECR2 registers by setting CCR6.2 to a logic 1.
Receive Clock. Buffered recovered clock from the line. Synchronous to
MCLK in absence of signal at RTIP and RRING.
Receive Carrier Loss/Loss of Transmit Clock. An output which will
toggle high during a receive carrier loss (CCR2.7 = 0) or will toggle high
if the TCLK pin has not been toggled for 5 µs ± 2 µs (CCR2.7 = 1).
CCR2.7 defaults to logic 0 when in hardware mode.
Receive Negative Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with the bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section
for details.
Receive Positive Data. Updated on the rising edge (CCR2.0 = 0) or the
falling edge (CCR2.0 = 1) of RCLK with bipolar data out of the line
interface. Set NRZE (CCR1.6) to a one for NRZ applications. In NRZ
mode, data will be output on RPOS while a received error will cause a
positive-going pulse synchronous with RCLK at RNEG. See Section
for details.
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These
pins connect via a 1:1 transformer to the line. See Section
Serial Clock. Serial bus clock input.
20
-1 PRBS depending on the ETS bit setting (CCR1.7). Remains
for details.
15 of 73
FUNCTION
5
for details.
15
-1
6.4
6.4