CDB5368 Cirrus Logic Inc, CDB5368 Datasheet - Page 10

• Manufacturer Part Number: CDB5368
• Description: BOARD EVAL FOR CS5368 192KHZ ADC
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5368

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Inputs Per Adc: 8 Differential
• Input Range: ±0.3 V
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5368
• Description/function: Audio A/D
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS5368
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1157

10
4.2
4.3
4.4
.
.
.
Switches
The CDB5368 Evaluation Board switches are used for setting speed modes and format protocols and for
resetting devices to their default state. The switch functions are described in
User Configuration Jumpers
The CDB5368 Evaluation Board jumpers are used for signal routing as shown in
Reserved Factory Programming Jumpers
The CDB5368 Evaluation Board has two reserved headers, J15 and J8, that are used to factory program
the Cygnal
Caution! Do not apply power or shorts to these two jumpers as device damage could occur.
J7
J91
J85
J11
J9
J4
S1-1
S1-2
S1-3
S1-4
S1-5
S1-6
S4-1
S4-2
S3
S2
J15
J8
DESIGNATOR
DESIGNATOR
DESIGNATOR
®
8051 microprocessor and the Xilinx® FPGA so that the FlexGUI interface operates correctly.
CONTROL
-
-
OSC/XTL
+5 V/VA EXT
DSP HEADER
M0
M1
DIF0
DIF1
TDM0
TDM1
MDIV
CLKMODE
BOARD RESET
PGM
MICRO_PROG
JTAG
NAME
NAME
NAME
Table 4. CDB5368 Reserved Jumpers
Table 2. CDB5368 Switches
Table 3. User Jumpers
Select I²C control Source
Short to ground when not using Crystal
Short to ground when not using Crystal
Canned Oscillator/Crystal Selection
VA source selector
speed mode; Master/Slave function
speed mode; Master/Slave function
Data Format
Data Format
Select Channel pairs for S/PDIF output
Select Channel pairs for S/PDIF output
Master Clock Divider
Master Clock Divider
Resets CS5368, CS8406 and FPGA
Forces FPGA to be loaded with new code (not needed by
user)
Reserved interface for pre-programming the Evaluation Board
Reserved interface for pre-programming the Evaluation Board
FUNCTION (see CS5368 Datasheet for details)
FUNCTION
FUNCTION
Table
Table 3
2.
DS624DB1
CDB5368