CDB5560 Cirrus Logic Inc, CDB5560 Datasheet - Page 6

• Manufacturer Part Number: CDB5560
• Description: DEV BOARD FOR CS5560 W/MUX
• Manufacturer: Cirrus Logic Inc
• Type: A/Dr

Specifications of CDB5560

• Number Of Adc's: 1
• Number Of Bits: 24
• Sampling Rate (per Second): 50k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±3 V
• Power (typ) @ Conditions: 90mW @ 2.5 V
• Voltage Supply Source: Dual ±
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS5560
• Product: Data Conversion Development Tools
• Conversion Rate: 50 KSPS
• Resolution: 24 bit
• Maximum Clock Frequency: 16 MHz
• Interface Type: SPI
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): - 2.5 V
• For Use With/related Products: CS5560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1273; CDB5560-1

SWITCHING CHARACTERISTICS
T
VL - VLR = 3.3 V, ±5%, 2.5 V, ±5%, or 1.8 V, ±5%
Input levels: Logic 0 = 0V = Low; Logic 1 = VD+ = High; CL = 15 pF.
6
Master Clock Frequency
Master Clock Duty Cycle
Reset
RST Low Time
RST rising to RDY falling
Conversion
CONV Pulse Width
BP/UP setup to CONV falling
CONV low to start of conversion
Perform Single Conversion (CONV high before RDY falling)
Conversion Time
Sleep Mode
A
= -40 to +85 °C; V1+ = V2+ = +2.5 V, ±5%; V1- = V2- = -2.5 V, ±5%;
7. BP/UP can be changed coincident CONV falling. BP/UP must remain stable until RDY falls.
8. If CONV is held low continuously, conversions occur every 320 MCLK cycles.
9. RDY will fall when the device is fully operational when coming out of sleep mode.
If RDY is tied to CONV, conversions will occur every 322 MCLKs.
If CONV is operated asynchronously to MCLK, a conversion may take up to 324 MCLKs.
RDY falls at the end of conversion.
SLEEP low to low-power state
SLEEP high to device active (Note 9)
Parameter
Start of Conversion to RDY falling
Internal Oscillator
Internal Oscillator
External Clock
External Clock
(Note 7)
(Note 8)
5/4/09
Symbol
t
t
XIN
t
t
t
t
t
t
t
f
wup
cpw
bus
buh
con
con
scn
scn
res
clk
Min
0.5
12
40
20
1
4
0
-
-
-
-
-
-
1536
3083
Typ
120
14
16
50
-
-
-
-
-
-
-
Max
16.2
324
16
60
2
-
-
-
-
-
-
-
-
CS5560
DS713PP2
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MCLKs
MHz
MHz
Unit
µs
µs
ns
µs
%