EVAL-AD7694CBZ Analog Devices Inc, EVAL-AD7694CBZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-AD7694CBZ
• Description: BOARD EVALUATION FOR AD7694
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7694CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 250k
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 6.3mW @ 250kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7694
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TYPICAL CONNECTION DIAGRAM
Figure 20 shows an example of the recommended application
diagram for the AD7694.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7694 input
structure. The two diodes, D1 and D2, provide ESD protection
for the analog inputs, IN+ and IN−. Care must be taken to
ensure that the analog input signal never exceeds the supply
rails by more than 0.3 V, because this will cause these diodes to
become forward-biased and start conducting current. However,
these diodes can handle a forward-biased current of 130 mA
maximum. For instance, these conditions could eventually
occur when the input buffer’s (U1) supplies are different from
VDD. In such a case, an input buffer with a short-circuit,
current limitation can be used to protect the part.
This analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected. For instance, by using IN− to sense a remote signal
ground, ground potential differences between the sensor and
the local ADC ground are eliminated. During the acquisition
phase, the impedance of the analog input IN+ can be modeled
as a parallel combination of the capacitor C
formed by the series connection of R
the pin capacitance. R
component made up of some serial resistors and the on
resistance of the switches. C
OR IN–
GND
IN+
Figure 21. Equivalent Analog Input Circuit
C
PIN
NOTES
1. SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2. C
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
0 TO V
IN
VDD
is typically 600 Ω and is a lumped
REF
D1
D2
REF
(NOTE 3)
IS USUALLY A 10μF CERAMIC CAPACITOR (X5R).
IN
is typically 30 pF and is mainly
IN
and C
R
IN
(NOTE 1)
PIN
REF
IN
(NOTE 4)
2.7nF
and the network
33Ω
. C
C
PIN
IN
2.2 TO 10μF
is primarily
Figure 20. Typical Application Diagram
(NOTE 2)
Rev. A | Page 13 of 16
IN+
IN–
REF
GND
AD7694
the ADC sampling capacitor. During the conversion phase,
where the switches are opened, the input impedance is limited
to C
undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7694 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance.
DRIVER AMPLIFIER CHOICE
Although the AD7694 is easy to drive, the driver amplifier
needs to meet the following requirements:
•
•
•
PIN
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7694. Note that the AD7694
has a noise much lower than most of the other
16-bit ADCs and, therefore, can be driven by a noisier op
amp while preserving the same or better system perfor-
mance. The noise coming from the driver is filtered by the
AD7694 analog input circuit 1-pole, low-pass filter made
by R1 and C2 or by the external filter, if one is used.
For ac applications, the driver needs to have a THD
performance suitable to that of the AD7694. Figure 13
gives the THD vs. frequency that the driver should exceed.
For multichannel, multiplexed applications, the driver
amplifier and the AD7694 analog input circuit must be
able to settle for a full-scale step of the capacitor array at a
16-bit level (0.0015%). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This could
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
VDD
. R
IN
SDO
SCK
CNV
and C
100nF
IN
make a 1-pole, low-pass filter that reduces
3-WIRE INTERFACE
2.7V TO 5.25V
AD7694