CDB5364 Cirrus Logic Inc, CDB5364 Datasheet
CDB5364
Specifications of CDB5364
Related parts for CDB5364
CDB5364 Summary of contents
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... Ain- Buffers http://www.cirrus.com Description The CDB5364 evaluation board is an excellent means for quickly evaluating the CS5364 24-bit, 192 kHz A/D converter. Evaluation requires only a digital signal ana- lyzer, an analog signal source, and a power supply. On-board DIP switches configure the CS5364 in Stand- Alone mode, avoiding the need for a PC ...
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... Figure 11. Analog Inputs (Schematic page 8) ................................................................................. 19 Figure 12. Power (Schematic page 9) ....................................................................................................... 20 Figure 13. Top Silkscreen ......................................................................................................................... 21 Figure 14. Top Layer ................................................................................................................................. 22 Figure 15. Bottom Layer ............................................................................................................................ 23 LIST OF TABLES Table 1. CDB5364 Input and Output Connectors ....................................................................................... 9 Table 2. CDB5364 Switches ..................................................................................................................... 10 Table 3. User Jumpers .............................................................................................................................. 10 Table 4. CDB5364 Reserved Jumpers ..................................................................................................... 10 2 CDB5364 DS625DB1 ...
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... Standard analog input and digital output connectors are included for quick and reliable board setup. An on-board FPGA is used for configuring the various modes of the CS5364. Graphical User Interface software is supplied by Cirrus Logic, which allows programming the CDB5364 when connected to a host PC running ® ...
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... In PCM mode, TDM1 and TDM0 select which SDOUT is sent to the CS8406. 0x00 SDOUT1 (Channel 1, 2) 0x01 SDOUT2 (Channel 3, 4) 0x1x Reserved DIP Switch S4 contains two switches which function as described below.7 MDIV - divides the master clock by 2 when OPEN (HI). CLKMODE - divides the master clock by 1.5 when OPEN (HI) 4 CDB5364 DS625DB1 ...
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... FlexLoader.exe file. Hardware interface to the FlexGUI is provided by connecting an RS-232 cable or a USB cable between a host PC and the CDB5364. Once the FlexGUI is loaded, the Evaluation Board DIP switches are ignored, and all register settings are available for reading and writing using software control ...
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... When switching to TDM mode, the CS8406 Clock and Date source (Board Control Panel) must be changed prior to changing the CS5364 SAI format. This sequential ordering resets the FPGA to assure that it timed properly with the CS5364 TDM packet stream. 6 Figure Figure 1. Hi-Level FlexGUI View CDB5364 1. This view provides functionally DS625DB1 ...
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... When placed back in Stand-Alone mode, the DIP switches regain board control. Exiting Control Port mode is achieved by stopping the FlexGUI program. Once the program is stopped, about three seconds later, Stand-Alone mode is established. DS625DB1 Figure 2. FlexGUI Low-Level Register View CDB5364 7 ...
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... Quad Speed Master 0x11 Slave all speed AudioFMT1,0 set the Serial Audio Interface format when attaching the Serial Audio Interface of the DSP header to external equipment. 0x00 Left Justified 0x01 I²S 0x10 TDM 2-wire 0x11 TDM 4-wire 8 Figure 3. FPGA Low-Level Bit View CDB5364 DS625DB1 ...
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... Clock Source is the FPGA TDM2PCM engine 4. CDB5364 HARDWARE The CDB5364 Evaluation Board has a number of connections, switches and jumpers that provide ease and conve- nience for quickly evaluating the most commonly used functions of the CS5364 silicon device. The following tables list the purpose of each hardware option on the Evaluation Board ...
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... J4 DSP HEADER 4.4 Reserved Factory Programming Jumpers The CDB5364 Evaluation Board has two reserved headers, J15 and J8, that are used to factory program ® the Cygnal 8051 microprocessor and the Xilinx® FPGA so that the FlexGUI interface operates correctly. Caution! Do not apply power or shorts to these two jumpers as device damage could occur. ...
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... Grounding and Power Supply Treatment As a high-peformance mixed-signal device, the CS5364 requires careful attention to power and grounding arrangements to optimize CS5364 performance. The CDB5364 Evaluation Board provides an excellent ref- erence example of an optimum two-layer board layout that places decoupling capacitors as close to the CS5364 as possible and provides ground plane fill on both top and bottom layers ...
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SCHEMATICS Figure 4. CS5364 (Schematic page 1) ...
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Figure 5. Clock Generation (Schematic page 2) ...
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Figure 6. FPGA (Schematic page 3) ...
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Figure 7. Control Port (Schematic page 4) ...
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Figure 8. Clock and Data Buffers (Schematic page 5) ...
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S/PDIF Figure 9. CD8406 Output (Schematic page 6) ...
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Figure 10. Analog Inputs (Schematic page 7) ...
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Figure 11. Analog Inputs (Schematic page 8) ...
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Figure 12. Power (Schematic page 9) ...
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BOARD LAYOUT AND ROUTING PLOTS Figure 13. Top Silkscreen ...
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Figure 14. Top Layer ...
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Figure 15. Bottom Layer ...
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... Cirrus Logic, Cirrus, and the Cirrus Logic logo and designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. Microsoft Windows is a registered trademark of Microsoft Corporation. Cygnal is a registered trademark of Silicon Laboratories, Inc. Xilinx is a registered trademark of Xilinx, Inc. 24 Changes Initial Release CDB5364 DS625DB1 ...