ADC108S052EVAL National Semiconductor, ADC108S052EVAL Datasheet - Page 13

• Manufacturer Part Number: ADC108S052EVAL
• Description: BOARD EVALUATION FOR ADC108S052
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC108S052EVAL

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 7.5mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC108S052
• Lead Free Status / RoHS Status: Not applicable / Not applicable

1.0 Functional Description
The ADC108S052 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter.
1.1 ADC108S052 OPERATION
Simplified schematics of the ADC108S052 in both track and
hold operation are shown in
tively. In
SW1 connects the sampling capacitor to one of eight analog
input channels through the multiplexer, and SW2 balances
the comparator inputs. The ADC108S052 is in this state for
the first three SCLK cycles after CS is brought low.
1.2 SERIAL INTERFACE
An operational timing diagram and a serial interface timing
diagram for the ADC108S052 are shown in The Timing Dia-
grams section. CS, chip select, initiates conversions and
frames the serial data transfers. SCLK (serial clock) controls
both the conversion process and the timing of serial data.
DOUT is the serial data output pin, where a conversion result
is sent as a serial data stream, MSB first. Data to be written
to the ADC108S052's Control Register is placed on DIN, the
serial data input pin. New data is written to DIN with each
conversion.
A serial frame is initiated on the falling edge of CS and ends
on the rising edge of CS. Each frame must contain an integer
multiple of 16 rising SCLK edges. The ADC's DOUT pin is in
a high impedance state when CS is high and is active when
CS is low. Thus, CS acts as an output enable. Similarly, SCLK
is internally gated off when CS is brought high.
Figure
4, the ADC108S052 is in track mode: switch
Figure 4
and
Figure 5
FIGURE 4. ADC108S052 in Track Mode
FIGURE 5. ADC108S052 in Hold Mode
respec-
13
Figure 5
connects the sampling capacitor to ground, maintaining the
sampled voltage, and switch SW2 unbalances the compara-
tor. The control logic then instructs the charge-redistribution
DAC to add or subtract fixed amounts of charge to or from the
sampling capacitor until the comparator is balanced. When
the comparator is balanced, the digital word supplied to the
DAC is the digital representation of the analog input voltage.
The ADC108S052 is in this state for the last thirteen SCLK
cycles after CS is brought low.
During the first 3 cycles of SCLK, the ADC is in the track
mode, acquiring the input voltage. For the next 13 SCLK cy-
cles the conversion is accomplished and the data is clocked
out. SCLK falling edges 1 through 4 clock out leading zeros,
falling edges 5 through 14 clock out the conversion result,
MSB first, and falling edges 15 and 16 clock out trailing zeros.
If there is more than one conversion in a frame (continuous
conversion mode), the ADC will re-enter the track mode on
the falling edge of SCLK after the N*16th rising edge of SCLK
and re-enter the hold/convert mode on the N*16+4th falling
edge of SCLK. "N" is an integer value.
The ADC108S052 enters track mode under three different
conditions. In
ADC enters track mode on the first falling edge of SCLK. In
the second condition, CS goes low with SCLK low. Under this
condition, the ADC automatically enters track mode and the
falling edge of CS is seen as the first falling edge of SCLK. In
the third condition, CS and SCLK go low simultaneously and
shows the ADC108S052 in hold mode: switch SW1
Figure
1, CS goes low with SCLK high and the
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