ADC108S052EVAL National Semiconductor, ADC108S052EVAL Datasheet - Page 15

• Manufacturer Part Number: ADC108S052EVAL
• Description: BOARD EVALUATION FOR ADC108S052
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC108S052EVAL

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 8 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 7.5mW @ 500kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC108S052
• Lead Free Status / RoHS Status: Not applicable / Not applicable

2.0 Applications Information
2.1 TYPICAL APPLICATION CIRCUIT
A typical application is shown in
digital supply pins are both powered in this example by the
National LP2950 low-dropout voltage regulator. The analog
supply is bypassed with a capacitor network located close to
the ADC108S052. The digital supply is separated from the
analog supply by an isolation resistor and bypassed with ad-
ditional capacitors. The ADC108S052 uses the analog supply
(V
2.2 POWER SUPPLY CONSIDERATIONS
There are three major power supply concerns with this prod-
uct: power supply sequencing, power management, and the
effect of digital supply noise on the analog supply.
2.2.1 Power Supply Sequence
The ADC108S052 is a dual-supply device. The two supply
pins share ESD resources, so care must be exercised to en-
sure that the power is applied in the correct sequence. To
avoid turning on the ESD diodes, the digital supply (V
not exceed the analog supply (V
even on a transient basis. Therefore, V
or concurrently with V
2.2.2 Power Management
The ADC108S052 is fully powered-up whenever CS is low
and fully powered-down whenever CS is high, with one ex-
ception. If operating in continuous conversion mode, the AD-
C108S052 automatically enters power-down mode between
SCLK's 16th falling edge of a conversion and SCLK's 1st
falling edge of the subsequent conversion (see
In continuous conversion mode, the ADC108S052 can per-
form multiple conversions back to back. Each conversion
requires 16 SCLK cycles and the ADC108S052 will perform
conversions continuously as long as CS is held low. Contin-
uous mode offers maximum throughput.
In burst mode, the user may trade off throughput for power
consumption by performing fewer conversions per unit time.
This means spending more time in power-down mode and
less time in normal mode. By utilizing this technique, the user
can achieve very low sample rates while still utilizing an SCLK
frequency within the electrical specifications. The Power Con-
sumption vs. SCLK curve in the Typical Performance Curves
section shows the typical power consumption of the AD-
A
) as its reference voltage, so it is very important that V
D
.
Figure
A
) by more than 300 mV, not
8. The split analog and
A
must ramp up before
FIGURE 8. Typical Application Circuit
Figure
D
) can-
1).
A
be
15
kept as clean as possible. Due to the low power requirements
of the ADC108S052, it is also possible to use a precision ref-
erence as a power supply.
To minimize the error caused by the changing input capaci-
tance of the ADC108S052, a capacitor is connected from
each input pin to ground. The capacitor, which is much larger
than the input capacitance of the ADC108S052 when in track
mode, provides the current to quickly charge the sampling
capacitor of the ADC108S052. An isolation resistor is added
to isolate the load capacitance from the input source.
C108S052. To calculate the power consumption (P
multiply the fraction of time spent in the normal mode (t
the normal mode power consumption (P
tion of time spent in shutdown mode (t
shutdown mode power consumption (P
9.
2.2.3 Power Supply Noise Considerations
The charging of any output load capacitance requires current
from the digital supply, V
the supply to charge the output capacitance will cause voltage
variations on the digital supply. If these variations are large
enough, they could degrade SNR and SINAD performance of
the ADC. Furthermore, if the analog and digital supplies are
tied directly together, the noise on the digital supply will be
coupled directly into the analog supply, causing greater per-
formance degradation than would noise on the digital supply
alone. Similarly, discharging the output capacitance when the
digital output goes from a logic high to a logic low will dump
current into the die substrate, which is resistive. Load dis-
charge currents will cause "ground bounce" noise in the sub-
strate that will degrade noise performance if that current is
large enough. The larger the output capacitance, the more
current flows through the die substrate and the greater the
noise coupled into the analog channel.
FIGURE 9. Power Consumption Equation
D
. The current pulses required from
S
N
) as shown in
S
), and add the frac-
) multiplied by the
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C
), simply
Figure
N
) by