ADC122S706EB/NOPB National Semiconductor, ADC122S706EB/NOPB Datasheet - Page 3

• Manufacturer Part Number: ADC122S706EB/NOPB
• Description: BOARD EVAL FOR ADC122S706
• Manufacturer: National Semiconductor

Specifications of ADC122S706EB/NOPB

• Number Of Adc's: 2
• Number Of Bits: 12
• Sampling Rate (per Second): 1M
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 25mW @ 1MSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: ADC122S706
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC122S706EB

Pin Descriptions and Equivalent Circuits
Pin No.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Symbol
CHA+
CHA−
CHB−
CHB+
D
D
DUAL
SCLK
GND
GND
V
CS
V
OUTA
OUTB
V
REF
A
D
Voltage Reference Input. A voltage reference between 1V and V
input. V
µF. A bulk capacitor value of 1.0 µF to 10 µF in parallel with the 0.1 µF is recommended
for enhanced performance.
Non-Inverting Input for Channel A. CHA+ is the positive analog input for the differential
signal applied to Channel A.
Inverting Input for Channel A. CHA− is the negative analog input for the differential signal
applied to Channel A.
Ground. GND is the ground reference point for all signals applied to the ADC122S706.
Inverting Input for Channel B. CHB− is the negative analog input for the differential signal
applied to Channel B.
Non-Inverting Input for Channel B. CHB+ is the positive analog input for the differential
signal applied to Channel B.
Analog Power Supply input. A voltage source between 4.5V and 5.5V must be applied to
this input. V
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Applying a logic high to this pin causes the conversion result of Channel A to be output
on D
pin causes the conversion result of Channel A and B to be output on D
of Channel A being output first. D
grounded.
Ground. GND is the ground reference point for all signals applied to the ADC122S706.
Digital Power Supply input. A voltage source between 2.7V and V
this input. V
parallel with a bulk capacitor value of 1.0 µF to 10 µF.
Serial Data Output for Channel A. With DUAL at a logic high state, the conversion result
for Channel A is provided on D
bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling
edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state,
the conversion result of Channel A and B is outputted on D
Serial Data Output for Channel B. With DUAL at a logic high state, the conversion result
for Channel B is provided on D
bits and 12 data bits (MSB first). During a conversion, the data is outputted on the falling
edges of SCLK and is generally valid on the rising edges. With DUAL at a logic low state,
D
Serial Clock. SCLK is used to control data transfer and serves as the conversion clock.
Chip Select Bar. CS is active low. The ADC122S706 is in Normal Mode when CS is LOW
and Power-Down Mode when CS is HIGH. A conversion begins on the fall of CS.
OUTB
OUTA
is in a high impedance state.
REF
and the conversion result of Channel B to be output on D
must be decoupled to GND with a minimum ceramic capacitor value of 0.1
A
D
must be decoupled to GND with a ceramic capacitor value of 0.1 µF in
must be decoupled to GND with a ceramic capacitor value of 0.1 µF in
3
OUTA
OUTB
OUTB
. The serial data output word is comprised of 4 null
. The serial data output word is comprised of 4 null
Description
is in a high impedance state when DUAL is
OUTA
.
A
must be applied to this
A
OUTB
must be applied to
OUTA
. Grounding this
, with the result
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