ADC08D1020DEV/NOPB National Semiconductor, ADC08D1020DEV/NOPB Datasheet - Page 4

• Manufacturer Part Number: ADC08D1020DEV/NOPB
• Description: BOARD DEV FOR ADC08D1020
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1020DEV/NOPB

• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.6W @ 1GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1020
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1020DEV

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Pin Functions
Pin No.
Pin Descriptions and Equivalent Circuits
29
15
26
30
3
4
OutEdge / DDR /
OutV / SCLK
DCLK_RST /
DCLK_RST+
Symbol
SDATA
PDQ
CAL
PD
Equivalent Circuit
4
Output Voltage Amplitude and Serial Interface Clock. Tie this
pin high for normal differential DCLK and data amplitude.
Ground this pin for a reduced differential output amplitude
and reduced power consumption. See
Outputs. When the extended control mode is enabled, this
pin functions as the SCLK input which clocks in the serial
data. See
on the extended control mode. See
INTERFACE
Power Down Pins. A logic high on the PD pin puts the entire
device into the Power Down Mode.
DCLK Edge Select, Double Data Rate Enable and Serial
Data Input. This input sets the output edge of DCLK+ at
which the output data transitions. (See
Demultiplex Control
connected to 1/2 the supply voltage, DDR clocking is
enabled. When the extended control mode is enabled, this
pin functions as the SDATA input. See
EXTENDED CONTROL
mode. See
the serial interface.
DCLK Reset. When single-ended DCLK_RST is selected by
floating or setting pin 52 logic high, a positive pulse on this
pin is used to reset and synchronize the DCLK outputs of
multiple converters. See
SYNCHRONIZATION
differential DCLK_RST is selected by setting pin 52 logic low,
this pin receives the positive polarity of a differential pulse
signal used to reset and synchronize the DCLK outputs of
multiple converters.
A logic high on the PDQ pin puts only the "Q" ADC into the
Power Down mode.
Calibration Cycle Initiate. A minimum 1280 input clock cycles
logic low followed by a minimum of 1280 input clock cycles
high on this pin initiates the calibration sequence. See
Calibration
Command Calibration
calibration.
1.2 NORMAL/EXTENDED CONTROL
1.3 THE SERIAL INTERFACE
for an overview of calibration and
for description of the serial interface.
Setting). When this pin is floating or
for detailed description. When
for a description of on-command
Description
for details on the extended control
1.5 MULTIPLE ADC
1.3 THE SERIAL
1.1.6 The LVDS
1.1.5.2 OutEdge and
1.2 NORMAL/
for description of
2.4.2.2 On-
for details
2.4.2