ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 18

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ADC08D1500DEV/NOPB

Manufacturer Part Number
ADC08D1500DEV/NOPB
Description
BOARD DEV FOR ADC08D1500
Manufacturer
National Semiconductor
Series
PowerWise®r

Specifications of ADC08D1500DEV/NOPB

Mfg Application Notes
Clocking High-Speed A/D Converters AppNote
Number Of Adc's
2
Number Of Bits
8
Sampling Rate (per Second)
1.5G
Data Interface
Serial
Inputs Per Adc
1 Differential
Input Range
870 mVpp
Power (typ) @ Conditions
1.8W @ 1.5GSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC08D1500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADC08D1500DEV

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADC08D1500DEV/NOPB
Manufacturer:
ELNA
Quantity:
30 000
18
Hardware/Serial Control
Hardware Pin Control – The ADC is controlled by the logic states on the dedicated control pins. The logic
on these pins is determined by the setting of OUTV, OUTEDGE, DDR, DES and FSR below.
Serial Register Program – The ADCs registers are accessed through the Extended Control Mode. In this
mode the hardware pin control is disabled and the programmable registers are available for fine tuning.
NOTE: The Following Pull-down Tabs are available only when Hardware Pin Control is selected.
Out V
Low Amplitude – LVDS output voltage amplitude is set to 510mV pk-pk.
High Amplitude – LVDS output voltage amplitude is set to 710mV pk-pk.
OutEdge
Falling Edge – Data outputs are changed on the falling edge of DCLK+ (Single Data rate mode only).
Rising Edge – Data outputs are changed on the rising edge of DCLK+ (Single Data rate mode only).
DDR
Disable Dual Data Rate – DDR Mode is disabled (data output follows OutEdge Setting).
Enable Dual Data Rate – Data is output with rising and falling edge of DCLK (Default for 1.5GHz clock).
DES
Disable Dual Edge Sample – DES Mode is disabled (I and Q are independent).
Enable Dual Edge Sample – The I channel is sampled on the rising and falling edge of the clock.
FSR
650mV Full Scale – Sets the full scale range to 650mV pk-pk.
870mV Full Scale – Sets the full scale range to 870mV pk-pk.
NOTE: The Following Pull-down Tabs are available regardless of Hardware/Serial Control setting.
Standby
Disable Standby – Enable all on-board power regulators.
Enable Standby – Board is put into standby mode – All power is shutdown except USB power.
PDQ
Disable Q Shutdown – The ADC’s Q Channel is powered up and Active.
Enable Q Shutdown – The ADC’s Q Channel is shutdown.
PD
Disable Shutdown – The ADC is powered up and Active.
Enable Shutdown – The ADC is put into low power mode. Register Settings are retained.

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