MAX1181EVKIT Maxim Integrated Products, MAX1181EVKIT Datasheet - Page 5

• Manufacturer Part Number: MAX1181EVKIT
• Description: EVAL KIT FOR MAX1181
• Manufacturer: Maxim Integrated Products

Specifications of MAX1181EVKIT

• Number Of Adc's: 1
• Number Of Bits: 10
• Sampling Rate (per Second): 80M
• Data Interface: Parallel
• Inputs Per Adc: 2 Differential
• Input Range: 2 Vpp
• Power (typ) @ Conditions: 246W @ 80MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: MAX1180, 1181, 1182, 1183, 1184, 1185, 1186, 1190
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX1181 requires an input voltage reference at its
REFIN pin to set the full-scale analog signal voltage
input. The ADC has a stable on-chip voltage reference of
2.048V that can be accessed at REFOUT. The EV kit was
designed to use the on-chip voltage reference by con-
necting REFIN to REFOUT through resistor R20. The user
can externally adjust the reference level, and hence the
full-scale range, by installing a resistor at the R19 pad.
The adjusted reference level can be calculated by
applying the following equation:
where R19 is the value of the resistor installed, R20 is a
10kΩ resistor, and V
user can apply a stable, low noise, external voltage ref-
erence directly at the REFIN pad to set the full scale.
Table 3. Output Format
Table 4. Output Bit Location (Nonmultiplexed/Multiplexed Output Operation)
*For multiplexed output operation, Channel A and Channel B data is captured with a single 10-bit bus. Leave header designators
J25 (B1) through J41 (B9) open.
CHANNEL
NONMULTIPLEXED OUTPUT OPERATION
MULTIPLEXED OUTPUT OPERATION*
JUMPER
CLK ↑
CLK ↑
CLK ↓
CLK ↑
JU5
A
B
A
B
V
REFIN
STATE
J1-23
J1-23
A/B
SHUNT STATUS
N/A
N/A
1
0
1 and 2
2 and 3
_______________________________________________________________________________________
=
REFOUT



BIT D0
R
J1-19
J1-23
J1-19
J1-19
A0
B0
A0
A0
19
R
19
+
R
is 2.048V. Alternatively, the
20
BIT D1
Reference Voltage
J1-17
J1-25
J1-17
J1-17

 ×

T/B connected to VDDUT
T/B connected to DGND
A1
B1
A1
A1
V
REFOUT
BIT D2
J1-15
J1-27
J1-15
J1-15
A2
B2
A2
A2
PIN CONNECTION
BIT D3
J1-13
J1-29
J1-13
J1-13
A3
B3
A3
A3
MAX1181 Evaluation Kit
BIT D4
The MAX1181 features two 10-bit, parallel, CMOS-com-
patible, digital outputs channels (Channels A and B).
The digital output coding can be chosen to be either in
two’s complement format or straight offset binary format
by configuring jumper JU5. Refer to Table 3 for jumper
configuration. Two drivers buffer the ADC’s Channel A
and B digital outputs. The buffer is able to drive large
capacitive loads, which may be present at the logic
analyzer connection, without compromising the digital
output signal. The outputs of the buffers are connected
to a 50-pin header (J1) located on the right side of the
EV kit, where the user can connect a logic analyzer or
data-acquisition system. Refer to Table 4 for channel
and bit location on header J1.
J1-11
J1-31
J1-11
J1-11
A4
B4
A4
A4
BIT D5
J1-33
J1-9
J1-9
J1-9
A5
B5
A5
A5
Digital output in two's complement
Digital output in straight offset binary
BIT D6
J1-35
J1-7
J1-7
J1-7
A6
B6
A6
A6
EV KIT OPERATION
BIT D7
J1-37
J1-5
J1-5
J1-5
A7
B7
A7
A7
Output Signal
BIT D8
J1-39
J1-3
J1-3
J1-3
A8
B8
A8
A8
BIT D9
J1-41
J1-1
J1-1
J1-1
A9
B9
A9
A9
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