LM4930LQBD National Semiconductor, LM4930LQBD Datasheet - Page 5

• Manufacturer Part Number: LM4930LQBD
• Description: BOARD EVALUATION LM4930LQ
• Manufacturer: National Semiconductor
• Series: Boomer®r

Specifications of LM4930LQBD

• Amplifier Type: Class AB
• Output Type: 1-Channel (Mono) with Stereo Headphones
• Max Output Power X Channels @ Load: 1W x 1 @ 8 Ohm; 27mW x 2 @ 32 Ohm
• Voltage - Supply: 2.6 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: LM4930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

System Control Registers
The LM4930 is controlled with a two-wire serial interface.
This interface is used to configure the operating mode, digi-
tal interfaces, and delta-sigma modulators. The LM4930 is
BIT
RESET
Address
3:0
4
5
6
7
8:9
10
11
12
13
14
15
This register is used to configure the I
BASICCONFIG register is XX10000.
BASIC CONFIGURATION (XX1000). (Set = logic 1, Clear = logic 0)
15
0
Register
MODE
SOFT_RESET
PCM_LONG
PCM_COMPANDED
PCM_LAW
PCM_SYNC_MODE
PCM_ALWAYS_ON
I2S_M/S
I2S_RES
RSVD
RSVD
RSVD
14
0
13
0
Description
The LM4930 can be placed in one of several modes that dictate the basic operation. When a
new mode is selected the LM4930 will change operation silently and will re-configure the
power management profile automatically. The modes are described as follows: (Note 14)
Mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
Resets the LM4930, excluding the control registers
If set the PCM interface uses a long frame sync. (Note 12)
If set the 8 MSBs are presumed to be companded data and the 8 LSBs are ignored. (Note
12)
If set, the companded G711 data is set to be A-law, else µ-law is assumed (Note 12)
Sets 1 (00h), 2 (01h) or 4(10h) 16 bit frames per sync. The PCM_SDO pin is tri-stated during
the latter frames. (Note 12)
This bit should be set if another codec is using the PCM bus. When set, the LM4930 will
drive the clock and sync signals in all modes except Powerdown (Note 12)
I2S master or slave select. If set then I2S = master. Cleared = slave
I2S resolution select. If set then 32 bits per frame. If cleared then 16 bits per frame
RESERVED (Note 13)
RESERVED (Note 13)
RESERVED (Note 13)
2
S and PCM interfaces as well as the 48kHz DAC module. The 7 bit address for the
(X = 0 if ADDR is set to logic 0)
12
0
BASIC CONFIG REGISTER
11
0
Mono Speaker
Amplifier Source
None
None
Voice
None
Voice
Audio (L+R)
None
Audio (L+R)
Audio (Left)
Voice + Audio
(Left)
Voice
10
0
9
0
5
controlled by writing information into a series of write-only
registers, each with its own unique 7 bit address. The follow-
ing registers are programmable:
8
0
Headphone Left
Source
None
None
None
Voice
Voice
None
Audio (Left)
Audio (Left)
Voice
Voice
Audio (Left)
(X = 1 if ADDR is set to logic 1)
7
0
6
0
5
0
Headphone Right
Source
None
None
None
Voice
Voice
None
Audio (Right)
Audio (Right)
Voice
Voice
Audio (Left)
4
0
3
0
2
0
Comment
Powerdown mode
Standby mode
Mono speaker
mode
Headphone call
mode
Conference call
mode
L+R mixed to
mono speaker
Headphone
stereo audio
L+R mixed to
mono speaker +
stereo headphone
audio
Mixed Mode
Mixed mode
Mixed Mode
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