KIT33701DWBEVB Freescale Semiconductor, KIT33701DWBEVB Datasheet - Page 13

• Manufacturer Part Number: KIT33701DWBEVB
• Description: KIT FOR 33701 POWER SUPPLY
• Manufacturer: Freescale Semiconductor
• Type: LDO Controllers & Regulatorsr

Specifications of KIT33701DWBEVB

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 2, Non-Isolated
• Voltage - Input: 2.8 ~ 6V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: MC34701
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: 34701

Table 4.
the typical application circuit (see
Analog Integrated Circuit Device Data
Freescale Semiconductor
BOOST REGULATOR
LINEAR REGULATOR (LDO)
RESET MONITOR (
SCA, SCL PIN, I
Notes
Boost Regulator MOSFET Maximum ON Time
Boost Regulator Control Loop Propagation Delay
Boost Switching Node VBD Rise Time
Boost Switching Node VBD Fall Time
Fault Condition Timeout
Retry Timer Cycle
Monitoring LFB Pin Delay
Monitoring INV Pin Delay
SCL Clock Frequency
Bus Free Time Between a STOP and a START Condition
Hold Time (Repeated) START Condition (After this period, the first clock
pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10pF to 400pF,
3.0mA Sink Current
Setup Time for a Repeated START Condition
Data Hold Time for I
Data Setup Time
Setup Time for STOP Condition
Capacitive Load for Each Bus Line
21.
22.
23.
Characteristics noted under conditions -40°C
IBST = 20mA
IBST = 20mA
Design information only. This parameter is not production tested.
The device provides an internal hold time of at least 300ns for the SDA signal (refer to the V
undefined region of the falling edge of SCL.
VIH is high level voltage on I
DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
2
C BUS (STANDARD)
(21)
RST
(21),
(21)
2
C Bus Devices
(21)
)
(23)
(21)
Characteristic
(21)
(21)
(21)
2
(21)
C bus lines and VIL is low level voltage on I
Figures
(21)
(21)
,
(22)
33), unless otherwise noted.
(21)
(21)
(21)
≤
T
A
(21)
≤
85°C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using
t
t
D_RST_LFB
D_RST_INV
2
Symbol
t
t
t
t
t
t
t
t
C bus lines
BST_PD
t
HD-DAT
SU-DA
SU-STO
B_FALL
HD-STA
SU-STA
B_RISE
FAULT
t
t
t
f
t
HIGH
t
LOW
RET
BUF
SCL
C
ON
t
F
B
T
DYNAMIC ELECTRICAL CHARACTERISTICS
Min
250
7.0
4.7
4.0
4.7
4.0
4.7
0.0
4.0
70
12
12
–
–
–
–
–
–
–
IH_MIN
ELECTRICAL CHARACTERISTICS
of the SCL signal) to bridge the
Typ
100
5.0
3.0
24
50
10
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
150
100
250
400
15
28
28
–
–
–
–
–
–
–
–
–
–
–
Unit
kHz
ms
ms
pF
µs
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
µs
34701
13