ISL6520EVAL1 Intersil, ISL6520EVAL1 Datasheet - Page 6

• Manufacturer Part Number: ISL6520EVAL1
• Description: EVALUATION BOARD 1 ISL6520
• Manufacturer: Intersil

Specifications of ISL6520EVAL1

• Mfg Application Notes: ISL6520(A) App Note
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 15A
• Voltage - Input: 4.5 ~ 5.5V
• Regulator Topology: Buck
• Frequency - Switching: 300kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6520
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -

Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R
to the COMP/OCSET pin because the internal current source is
only 20μA. Provide local V
GND pins. Locate the capacitor, C
the BOOT and PHASE pins. All components used for feedback
compensation should be located as close to the IC a practical.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V
the PHASE node. The PWM wave is smoothed by the output
filter (L
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6520) and the impedance networks Z
and Z
a closed loop transfer function with the highest 0dB crossing
frequency (f
is the difference between the closed loop phase at f
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
R
locating the poles and zeros of the compensation network:
F LC
1. Pick Gain (R
3. Place 2
4. Place 1
5. Place 2
6. Check Gain against Error Amplifier’s Open-Loop Gain.
2. Place 1
+5V
3
OUT
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
, C
=
FB
1
------------------------------------------ -
2π x
) is regulated to the Reference voltage level. The
O
COMP/OCSET
, C
. The goal of the compensation network is to provide
and C
ISL6520
2
ST
, and C
ND
ST
ND
0dB
GND
L O x C O
1
LAYOUT GUIDELINES
Zero Below Filter’s Double Pole (~75% F
Pole at the ESR Zero.
O
Zero at Filter’s Double Pole.
Pole at Half the Switching Frequency.
) and adequate phase margin. Phase margin
).
2
/R
3
) in Figure 7. Use these guidelines for
1
) for desired converter bandwidth.
BOOT
PHASE
VCC
C
BOOT
CC
+5V
decoupling between VCC and
F ESR
6
C
D
VCC
BOOT
1
=
------------------------------------------- -
2π x ESR x C O
E/A
as close as practical to
) is compared with
Q
+V
Q
1
2
IN
1
L
O
OSCET
C
O
0dB
LC
close
(EQ. 4)
1
IN
V
, R
and
IN
OUT
).
at
2
,
ISL6520
The modulator transfer function is the small-signal transfer
function of V
Gain and the output filter (L
break frequency at F
the modulator is simply the input voltage (V
peak-to-peak oscillator voltage ΔV
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
F
F
ΔV
7. Estimate Phase Margin - Repeat if Necessary.
Z1
Z2
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
OSC
=
=
----------------------------------- -
2π x R
------------------------------------------------------ -
2π x R
OSC
(
COMPARATOR
OUT
1
2
COMPENSATION DESIGN
1
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
V
x C
ISL6520
+
1
E/A
PWM
/V
R
1
3
Z
+
E/A
-
) x C
FB
-
+
COMP
LC
C
. This function is dominated by a DC
REFERENCE
1
REFERENCE
and a zero at F
3
C
+
-
2
O
DRIVER
DRIVER
R
F
F
and C
Z
2
P1
P2
IN
P2
=
=
OSC
FB
O
Z
-------------------------------------------------------- -
2π x R
----------------------------------- -
2π x R
with the capabilities of
FB
), with a double pole
ESR
.
PHASE
(PARASITIC)
V
C
IN
3
1
2
3
IN
L
Z
R
. The DC Gain of
O
IN
x
x C
1
) divided by the
1
R
⎛
⎜
⎝
ESR
C
--------------------- -
C
C
3
3
1
O
1
V
OUT
+
x C
April 3, 2007
C
2
V
2
FN9009.6
(EQ. 5)
⎞
⎟
⎠
OUT