HIP6004EVAL3 Intersil, HIP6004EVAL3 Datasheet - Page 7

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HIP6004EVAL3

Manufacturer Part Number
HIP6004EVAL3
Description
EVALUATION BOARD EMBED HIP6004
Manufacturer
Intersil
Datasheets

Specifications of HIP6004EVAL3

Main Purpose
DC/DC, Step Down
Outputs And Type
1, Non-Isolated
Voltage - Output
1.3 ~ 3.5V
Current - Output
14A
Voltage - Input
5 ~ 12V
Regulator Topology
Buck
Board Type
Fully Populated
Utilized Ic / Part
HIP6004
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Power - Output
-
Frequency - Switching
-
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C
and C
Locate the HIP6004 within 3 inches of the MOSFETs, Q1
and Q2. The circuit traces for the MOSFETs’ gate and
source connections from the HIP6004 must be sized to
handle up to 1A peak current.
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
VID4
VID3
VID2
VID1
VID0
HIP6004
O
each represent numerous physical capacitors.
FIGURE 5. DAC FUNCTION SCHEMATIC
PHASE
UGATE
LGATE
10.7kΩ
21.5kΩ
3.6kΩ
2.7kΩ
5.4kΩ
PGND
12kΩ
GROUND PLANES OR ISLANDS
REFERENCE
1.26V
BAND GAP
12kΩ
2.9kΩ
+
-
1.7kΩ
DAC
Q2
V
Q1
RETURN
IN
DACOUT
7
D2
FB
C
IN
+
L
-
O
ERROR
AMPLIFIER
C
O
V
OUT
COMP
IN
HIP6004
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C
close to the SS pin because the internal current source is
only 10μA. Provide local V
GND pins. Locate the capacitor, C
practical to the BOOT and PHASE pins.
Feedback Compensation
Figure 8 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
amplifier (Error Amp) output (V
oscillator (OSC) triangular wave to provide a pulse-width
modulated (PWM) wave with an amplitude of V
PHASE node. The PWM wave is smoothed by the output
filter (L
OUT
C
FIGURE 8. VOLTAGE-MODE BUCK CONVERTER
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
SS
SS
Δ
V
) is regulated to the Reference voltage level. The error
OSC
O
and C
HIP6004
OSC
GND
COMPENSATION DESIGN
LAYOUT GUIDELINES
COMPARATOR
O
ERROR
AMP
DETAILED COMPENSATION COMPONENTS
V
).
HIP6004
E/A
PWM
Z
+
-
COMP
BOOT
PHASE
VCC
FB
-
+
C
C1
BOOT
REFERENCE
CC
+12V
C2
DACOUT
+
-
R2
DRIVER
decoupling between VCC and
DRIVER
C
E/A
Z
D1
VCC
IN
) is compared with the
BOOT
FB
Z
FB
PHASE
as close as
V
+V
Q1
Q2
(PARASITIC)
IN
C3
IN
L
Z
R1
L
O
IN
O
IN
C
R3
ESR
O
C
at the
O
V
OUT
V
V
ss
OUT
OUT

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