MAX5060EVKIT Maxim Integrated Products, MAX5060EVKIT Datasheet - Page 19

• Manufacturer Part Number: MAX5060EVKIT
• Description: EVAL KIT FOR MAX5060
• Manufacturer: Maxim Integrated Products

Specifications of MAX5060EVKIT

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 3.3V
• Current - Output: 20A
• Voltage - Input: 10 ~ 14V
• Regulator Topology: Buck
• Frequency - Switching: 270kHz
• Board Type: Fully Populated
• Utilized Ic / Part: MAX5060
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

The differential current-sense amplifier (CA) provides a
DC gain of 34.5. The maximum input offset voltage of
the current-sense amplifier is 1mV and the common-
mode voltage range is 0 to 5.5V (IN = 7V to 28V). The
current-sense amplifier senses the voltage across a
current-sense resistor. The maximum common-mode
voltage is 3.6V when V
age range determines the maximum output voltage of
the buck converter.
The peak-current comparator provides a path for fast
cycle-by-cycle current limit during extreme fault condi-
tions such as an output inductor malfunction (Figure 5).
Note the average current-limit threshold of 26.9mV still
limits the output current during short-circuit conditions.
To prevent inductor saturation, select an output inductor
with a saturation current specification greater than the
average current limit. Proper inductor selection ensures
that only the extreme conditions trip peak-current com-
parator, such as a broken output inductor. The 60mV
threshold for triggering the peak-current limit is twice the
full-scale average current-limit voltage threshold. The
peak-current comparator has only a 260ns delay.
The MAX5060/MAX5061 has a transconductance cur-
rent-error amplifier (CEA) with a typical g
and 320µA output sink- and source-current capability.
The current-error amplifier output CLP, serves as the
inverting input to the PWM comparator. CLP is external-
ly accessible to provide frequency compensation for
the inner current loops (Figure 5). Compensate (CEA)
so the inductor current down slope, which becomes the
up slope to the inverting input of the PWM comparator,
is less than the slope of the internally generated voltage
ramp (see the Compensation section).
The PWM comparator (CPWM) sets the duty cycle for
each cycle by comparing the output of the current-error
amplifier to a 2V
cycle, an R-S flip-flop resets and the high-side driver
(DH) turns on. The comparator sets the flip-flop as soon
as the ramp voltage exceeds the CLP voltage, thus ter-
minating the ON cycle (Figure 5).
The differential amplifier (DIFF AMP) facilitates output-
voltage remote sensing at the load (Figure 5). It pro-
vides true-differential output voltage sensing while
rejecting the common-mode voltage errors due to high-
current ground paths. Sensing the output voltage
PWM Comparator and R-S Flip-Flop
Differential Amplifier (MAX5060)
Average-Current-Mode DC-DC Controllers
P-P
______________________________________________________________________________________
ramp. At the start of each clock
IN
Peak-Current Comparator
Current-Sense Amplifier
= 5V. The common-mode volt-
Current-Error Amplifier
0.6V to 5.5V Output, Parallelable,
m
of 550µS
directly at the load provides accurate load voltage
sensing in high-current environments. The VEA pro-
vides the difference between the differential amplifier
output (DIFF) and the desired output voltage. The dif-
ferential amplifier has a bandwidth of 3MHz. The differ-
ence between SENSE+ and SENSE- is regulated to
0.6V for the MAX5060. Connect SENSE+ to the center
of the resistive divider from the output to SENSE-.
Connect SENSE- to PGND near the load.
The VEA sets the gain of the voltage control loop. The
VEA determines the error between the differential
amplifier output and the internal reference voltage.
The VEA output clamps to 930mV relative to the inter-
nally generated common-mode voltage (V
thus limiting the maximum output current. The maxi-
mum average current-limit threshold is equal to the
maximum clamp voltage of the VEA divided by the gain
(34.5) of the current-sense amplifier. This results in
accurate settings for the average maximum current for
each phase. Set the VEA gain using R
Figures 1 and 2) for the amount of output voltage posi-
tioning required within the rated current range as dis-
cussed in the Adaptive Voltage Positioning section. The
finite gain of the VEA introduces an error in the output
voltage setting. Use the following equation to calculate
the output voltage at no load condition.
MAX5060:
where R
(see the Typical Application Circuits) and V
MAX5061:
The error amplifier output (EAOUT), which is compared
against the output of the current amplifier (CA), may not
reduce down to zero due to the saturation voltage of its
output stage. This requires the converter to be loaded
with a minimum load to prevent it from slipping out of
regulation. The minimum load requirement can be elim-
inated by adding some DC bias voltage between CSP
and CSN. See the Typical Application Circuit (Figure 2).
Use RC1 and RC2 to generate approximately 3mV DC
bias at CSP with respect to CSN. Use the following
equation to calculate the values of RC1 and RC2.
V
RC
H
OUT NL
and R
1
(
( .
0 002
)
L
are the feedback resistor network
(
V
) ( .
1
CC
R
0 25
R
IN
F
Voltage-Error Amplifier
V
OUT
R
I
)
L
H
R
RC
L
R
R
SENSE
L
2
F
and R
V
REF
REF
)
CM
= 0.6V.
, 0.6V),
IN
(see
19