EVAL-AD5415EBZ Analog Devices Inc, EVAL-AD5415EBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD5415EBZ
• Description: BOARD EVALUATION FOR AD5415
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD5415EBZ

• Number Of Dac's: 2
• Number Of Bits: 12
• Outputs And Type: 2, Differential
• Sampling Rate (per Second): 2.47M
• Data Interface: Serial
• Settling Time: 120ns
• Dac Type: Current
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 125°C
• Utilized Ic / Part: AD5415
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD5415
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5415 DAC is through a
serial bus that uses standard protocol compatible with micro-
controllers and DSP processors. The communication channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5415 requires a 16-bit word,
with the default being data valid on the falling edge of SCLK;
however, this is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5415 Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5415 DAC without the need for extra glue logic. Figure 42
is an example of an SPI interface between the DAC and the
ADSP-2191. SCK of the DSP drives the serial data line, SDIN.
SYNC is driven from a port line, in this case SPIxSEL .
A serial interface between the DAC and DSP SPORT is shown
in Figure 43. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after SPORT is enabled. In a
write sequence, data is clocked out on each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
on the falling edge of its SCLK. The update of the DAC output
takes place on the rising edge of the SYNC signal.
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay
and data setup-and-hold, and SCLK width. The DAC interface
expects a t
of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame SYNC frequencies for the
SPORT register.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5415 Interface
ADSP-2101/
ADSP-2103/
ADSP-2191
ADSP-2191
4
1
SPIxSEL
( SYNC falling edge to SCLK falling edge setup time)
Figure 42. ADSP-2191 SPI-to-AD5415 Interface
1
SCLK
MOSI
SCK
TFS
DT
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5415
AD5415
1
1
Rev. B | Page 22 of 32
Table 12 shows the setup for the SPORT control register.
Table 12. SPORT Control Register Setup
Name
TFSW
INVTFS
DTYPE
ISCLK
TFSR
ITFS
SLEN
ADSP-BF5xx-to-AD5415 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI-
compatible devices. A serial interface between the BlackFin ®
processor and the AD5415 DAC is shown in Figure 44. In this
configuration, data is transferred through the MOSI (master
output, slave input) pin. SYNC is driven by the SPIxSEL pin,
which is a reconfigured programmable flag pin.
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 45. When SPORT is enabled,
initiate transmission by writing a word to the Tx register. The
data is clocked out on each rising edge of the DSP’s serial clock
and clocked into the DAC’s input shift register on the falling edge
of its SCLK. The DAC output is updated by using the transmit
frame synchronization (TFS) line to provide a SYNC signal.
1
1
ADDITIONAL PINS OMITTED FOR CLARITY.
ADDITIONAL PINS OMITTED FOR CLARITY.
ADSP-BF5xx
ADSP-BF5xx
SPIxSEL
Figure 45. ADSP-BF5xx SPORT-to-AD5415 Interface
Setting
1
1
1
1
1
1111
Figure 44. ADSP-BF5xx-to-AD5415 Interface
SCLK
MOSI
1
00
1
SCK
TFS
DT
Description
Alternate framing
Active low frame signal
Right-justify data
Internal serial clock
Frame every word
Internal framing signal
16-bit data-word
SYNC
SDIN
SCLK
SYNC
SDIN
SCLK
AD5415
AD5415
1
1