AD9717-EBZ Analog Devices Inc, AD9717-EBZ Datasheet - Page 39
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AD9717-EBZ
Manufacturer Part Number
AD9717-EBZ
Description
BOARD EVAL FOR AD9717
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet
1.AD9717BCPZ.pdf
(80 pages)
Specifications of AD9717-EBZ
Number Of Dac's
2
Number Of Bits
14
Outputs And Type
2, Differential
Sampling Rate (per Second)
125M
Data Interface
Serial
Dac Type
Current
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9717
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register
Memory R/W
CLKMODE
Version
Address
0x12
0x14
0x1F
Bit
7
6
4
3
2
1
0
7:6
4
3
2
1:0
7:0
Name
CALRSTQ
CALRSTI
CALEN
SMEMWR
SMEMRD
UNCALQ
UNCALI
CLKMODEQ[1:0]
Searching
Reacquire
CLKMODEN
CLKMODEI[1:0]
Version[7:0]
Description
0 (default): no action.
1: clear CALSTATQ.
0 (default): no action.
1: clear CALSTATI.
0 (default): no action.
1: initiate device self-calibration.
0 (default): no action.
1: write to static memory (calibration coefficients).
0 (default): no action.
1: read from static memory (calibration coefficients).
0 (default): no action.
1: reset Q DAC calibration coefficients to default (uncalibrated).
0 (default): no action.
1: reset I DAC calibration coefficients to default (uncalibrated).
Depending on the CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN, as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets Q clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Data path retimer status bit.
0 (default): clock relationship established.
1: indicates that the internal data path retimer is searching for clock relationship
(device output is not usable while this bit is high).
Edge triggered, 0 to 1 causes the retimer to reacquire the clock relationship.
0 (default): CLKMODEI/CLKMODEQ values computed by the two retimers and
read back in CLKMODEI[1:0] and CLKMODEQ[1:0].
1: CLKMODE values set in CLKMODEI[1:0] override both I and Q retimers.
Depending on CLKMODEN bit setting, these two bits reflect the phase
relationship between DCLKIO and CLKIN as described in Table 16.
If CLKMODEN = 0, read only; reports the clock phase chosen by the retimer.
If CLKMODEN = 1, read/write; value in this register sets I clock phases; force if
needed to better synchronize the DACs (see the Retimer section).
Hardware version of the device. This register is set to 0x03 for the latest version of
the device.
Rev. A | Page 39 of 80
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