LM5022LEDEVAL National Semiconductor, LM5022LEDEVAL Datasheet - Page 13

• Manufacturer Part Number: LM5022LEDEVAL
• Description: BOARD EVALUATION FOR LM5022
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5022LEDEVAL

• Current - Output / Channel: 1A
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 40V
• Features: Dimmable
• Voltage - Input: 10 ~ 14V
• Utilized Ic / Part: LM5022
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

For this example the small size and high temperature rating
of ceramic capacitors make them a good choice. The output
ripple voltage waveform of
pacitance will be selected first. The desired ΔV
40V, or 0.8V
required minimum capacitance is:
The next higher standard 20% capacitor value is 1.0 µF, how-
ever to provide margin for component tolerance and load
transients two capacitors rated 4.7 µF each will be used. Ce-
ramic capacitors rated 4.7 µF ±20% are available from many
manufacturers. The minimum quality dielectric that is suitable
for switching power supply output capacitors is X5R, while
X7R (or better) is preferred. Careful attention must be paid to
the DC voltage rating and case size, as ceramic capacitors
can lose 60% or more of their rated capacitance at the max-
imum DC voltage. This is the reason that ceramic capacitors
are often de-rated to 50% of their capacitance at their working
voltage. The output capacitors for this example will have a
100V rating in a 2220 case size.
The typical ESR of the selected capacitors is 3 mΩ each, and
in parallel is approximately 1.5 mΩ. The worst-case value for
ΔV
age:
The worst-case capacitor charging ripple occurs at maximum
duty cycle:
Finally, the worst-case value for ΔV
ripple current is highest, at maximum input voltage:
The output voltage ripple can be estimated by summing the
three terms:
O1
ΔV
occurs during the peak current at minimum input volt-
C
FIGURE 6. ΔV
O2
O-MIN
ΔV
= (0.5 / 9.4 x 10
ΔV
P-P
O3
C
= (0.5 / 0.8) x (0.77 / 5 x 10
O
. Beginning with the calculation for ΔV
O-MIN
= 0.58 x 0.0015 = 1 mV (negligible)
ΔV
= 4 mV + 82 mV - 1 mV = 85 mV
O1
= (I
= 2.5 x 0.0015 = 4 mV
O
Using Low ESR Capacitors
O
/ ΔV
-6
Figure 6
) x (0.77 / 5 x 10
O
) x (D
O3
is assumed, and the ca-
MAX
occurs when inductor
/ f
5
) = 0.96 µF
SW
5
) = 82 mV
)
20212227
O
is ±2% of
O2
, the
13
The RMS current through the output capacitor(s) can be es-
timated using the following, worst-case equation:
The highest RMS current occurs at minimum input voltage.
For this example the maximum output capacitor RMS current
is:
These 2220 case size devices are capable of sustaining RMS
currents of over 3A each, making them more than adequate
for this application.
VCC DECOUPLING CAPACITOR
The VCC pin should be decoupled with a ceramic capacitor
placed as close as possible to the VCC and GND pins of the
LM5022. The decoupling capacitor should have a minimum
X5R or X7R type dielectric to ensure that the capacitance re-
mains stable over voltage and temperature, and be rated to
a minimum of 470 nF. One good choice is a 1.0 µF device
with X7R dielectric and 1206 case size rated to 25V.
INPUT CAPACITOR
The input capacitors to a boost regulator control the input
voltage ripple, ΔV
transients, and prevent impedance mismatch (also called
power supply interaction) between the LM5022 and the in-
ductance of the input leads. Selection of input capacitors is
based on their capacitance, ESR, and RMS current rating.
The minimum value of ESR can be selected based on the
maximum output current transient, I
expression:
For this example the maximum load step is equal to the load
current, or 0.5A. The maximum permissable ΔV
transients is 4%
input voltage to give the worst-case value:
The minimum input capacitance can be selected based on
ΔV
based on prevention of power supply interaction. In general,
the requirement for greatest capacitance comes from the
power supply interaction. The inductance and resistance of
the input source must be estimated, and if this information is
not available, they can be assumed to be 1 µH and 0.1Ω, re-
spectively. Minimum capacitance is then estimated as:
As with ESR, the worst-case, highest minimum capacitance
calculation comes at the minimum input voltage. Using the
default estimates for L
IN
I
O-RMS(MAX)
, based on the drop in V
ESR
MIN
= [(1 – 0.77) x 0.36] / (2 x 0.5) = 83 mΩ
= 1.13 x 2.3 x (0.78 x 0.22)
P-P
. ΔV
IN
, hold up the input voltage during load
S
IN
and R
and duty cycle are taken at minimum
S
IN
, minimum capacitance is:
during a load transient, or
STEP
, using the following
0.5
= 1.08A
IN
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during load
RMS