LM5022LEDEVAL National Semiconductor, LM5022LEDEVAL Datasheet - Page 15

• Manufacturer Part Number: LM5022LEDEVAL
• Description: BOARD EVALUATION FOR LM5022
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5022LEDEVAL

• Current - Output / Channel: 1A
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 40V
• Features: Dimmable
• Voltage - Input: 10 ~ 14V
• Utilized Ic / Part: LM5022
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

One popular method for selecting the compensation compo-
nents is to create Bode plots of gain and phase for the power
stage and error amplifier. Combined, they make the overall
bandwidth and phase margin of the regulator easy to deter-
mine. Software tools such as Excel, MathCAD, and Matlab
are useful for observing how changes in compensation or the
power stage affect system gain and phase.
The power stage in a CCM peak current mode boost con-
verter consists of the DC gain, A
pole, f
and a double pole resulting from the sampling of the peak
current. The power stage transfer function (also called the
Control-to-Output transfer function) can be written:
Where the DC gain is defined as:
Where:
The system ESR zero is:
The low frequency pole is:
The right-half plane zero is:
LFP
FIGURE 7. Power Stage and Error Amp
, the ESR zero, f
R
O
ZESR
= V
, a right-half plane zero, f
O
/ I
PS
O
, a single low frequency
20212234
RHP
,
15
The sampling double pole quality factor is:
The sampling double corner frequency is:
The natural inductor current slope is:
The external ramp slope is:
In the equation for A
and output current are at the maximum. In this the example
those conditions are V
DC gain is 44 dB. The low frequency pole f
423Hz, the ESR zero f
half plane zero f
double-pole occurs at one-half of the switching frequency.
Proper selection of slope compensation (via R
ident the sampling double pole. A well-selected R
eliminates peaking in the gain and reduces the rate of change
of the phase lag. Gain and phase plots for the power stage
are shown in
S
e
Figure
= 45 µA x (2000 + R
RHP
PS
8.
S
= 2
, DC gain is highest when input voltage
n
IN
Z
ω
= R
= 2
= 16V and I
π
n
ω
=
SNS
π
RHP
π
ω
Z
x f
x V
is at 61 kHz. The sampling
is at 5.6 MHz, and the right-
SW
S1
IN
O
+ R
/ L
= 500 mA.
S2
)] x f
P
S2
SW
= 2
) is most ev-
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20212241
π
S2
ω
P
value
is at