LM3509SDEV National Semiconductor, LM3509SDEV Datasheet - Page 8

• Manufacturer Part Number: LM3509SDEV
• Description: BOARD EVALUATION FOR LM3509SD
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM3509SDEV

• Current - Output / Channel: 40mA
• Outputs And Type: 2, Non-Isolated
• Voltage - Output: 21V
• Features: Dimmable, I²C Interface
• Voltage - Input: 2.7 ~ 5.5V
• Utilized Ic / Part: LM3509
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Brightness Rate of Change
Description
RMP0 and RMP1 control the rate of change of the LED cur-
rent I
or BSUB. There are 4 user programmable LED current rates
of change settings for the LM3509 (see Table 5).
Table 5. Rate of Change Bits
The total time to transition from one brightness code to an-
other is:
Table 6. GPIO Register Function
RMP0
0
0
1
1
X
X
X
Bits 7 – 3
MAIN
and I
SUB/FB
X
Logic Input
Logic Output
Data (Bit 2)
RMP1
0
1
0
1
in response to changes in BMAIN and /
X
0
1
Mode (Bit 1)
Change Rate
(t
51µs/step
13ms/step
26ms/step
52ms/step
STEP
FIGURE 11. GPIO Register Description
)
0
1
1
Enable GPIO (Bit 0)
8
Where t
General Purpose I/O (GPIO)
RESET/GPIO has three functions; an active low reset input,
a logic input, and an open drain logic output. The default set-
ting is as an active low reset input. Write a '1' to bit 0 of the
GPIO register (address 0x80) to configure RESET/GPIO as
a general purpose I/O (GPIO). In this mode, bit 1 of the GPIO
register controls the input/output state of RESET/GPIO. With
bit 1 = '0', RESET/GPIO is configured as a logic input and the
data is read back via bit 2 of the GPIO register. With bit 1 =
'1', RESET/GPIO is configured as a logic output. In this mode
bit 2 of the GPIO register becomes the output data. Write a
'1' to bit 2 to force RESET/GPIO to a logic one. Write a '0' to
bit 2 to force RESET/GPIO to a logic zero. (see Table 6, and
figure 11) .
RESET/GPIO is configured as an active low reset
input. This is the default power on state.
RESET/GPIO is configured as a logic input. The logic
state applied to RESET/GPIO can be read via bit 2 of
the GPIO register.
RESET/GPIO is configured as a logic output. A 0 in
bit 2 forces RESET/GPIO low. A 1 in bit 2 forces
RESET/GPIO high impedance.
STEP
is given in Table 5.
30011113
Function