ISL9000GCEV2 Intersil, ISL9000GCEV2 Datasheet - Page 9

• Manufacturer Part Number: ISL9000GCEV2
• Description: EVAL BOARD 2.7V/1.8V ISL9000GC
• Manufacturer: Intersil

Specifications of ISL9000GCEV2

• Channels Per Ic: 2 - Dual
• Voltage - Output: 1.8V, 2.7V
• Current - Output: 300mA, 200mA
• Voltage - Input: 2.3 ~ 6.5 V
• Regulator Type: Positive Fixed
• Operating Temperature: -40°C ~ 85°C
• Board Type: Fully Populated
• Utilized Ic / Part: ISL9000
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Block Diagram
Functional Description
The ISL9000 contains two high performance LDOs. High
performance is achieved through a circuit that delivers fast
transient response to varying load conditions. In a quiescent
condition, the ISL9000 adjusts its biasing to achieve the
lowest standby current consumption.
The device also integrates current limit protection, smart
thermal shutdown protection, staged turn-on and soft-start.
Smart thermal shutdown protects the device against
overheating. Staged turn-on and soft-start minimize start-up
input current surges without causing excessive device
turn-on time.
Power Control
The ISL9000 has two separate enable pins, EN1 and EN2,
to individually control power to each of the LDO outputs.
When both EN1 and EN2 are low, the device is in shutdown
CBYP
VIN
EN1
EN2
LDO-1
UVLO
9
IS1
BANDGAP AND
TEMPERATURE
GENERATOR
REFERENCE
CONTROL
LDO-2
VOLTAGE
SENSOR
VREF
TRIM
LOGIC
QEN1
AMPLIFIER
ERROR
LDO
1V
COMPARATOR
1.00V
0.94V
0.90V
POR
ISL9000
CPOR
mode. During this condition, all on-chip circuits are off, and
the device draws minimum current, typically less than 0.1µA.
When one or both of the enable pins are asserted, the
device first polls the output of the UVLO detector to ensure
that VIN voltage is at least about 2.1V. Once verified, the
device initiates a start-up sequence. During the start-up
sequence, trim settings are first read and latched. Then,
sequentially, the bandgap, reference voltage and current
generation circuitry power-up. Once the references are
stable, a fast-start circuit quickly charges the external
reference bypass capacitor (connected to the CBYP pin) to
the proper operating voltage. After the bypass capacitor has
been charged, the LDOs power-up in their specified
sequence.
Soft-start circuitry integrated into each LDO limits the initial
ramp-up rate to about 30µs/V to minimize current surge.
VOK2
VOK1
~1.0V
GND
DELAY
DELAY
POR2
POR1
VOK1
POR1
VO1
VOK2
VO2
POR2
VO1
VO2
POR2
POR1
VO1
VO2
March 11, 2008
FN9217.4