ISL28213SOICEVAL2Z Intersil, ISL28213SOICEVAL2Z Datasheet - Page 15

• Manufacturer Part Number: ISL28213SOICEVAL2Z
• Description: EVALUATION BOARD FOR ISL28213
• Manufacturer: Intersil

Specifications of ISL28213SOICEVAL2Z

• Channels Per Ic: 2 - Dual
• Amplifier Type: General Purpose
• Output Type: Rail-to-Rail
• Slew Rate: 1 V/µs
• Current - Output / Channel: 22mA
• Operating Temperature: -40°C ~ 125°C
• Current - Supply (main Ic): 90µA
• Voltage - Supply, Single/dual (±): 2.4 V ~ 5.5 V, ±1.2 V ~ 2.75 V
• Board Type: Fully Populated
• Utilized Ic / Part: ISL28213
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -

Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to
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information page on intersil.com:
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12/16/09
11/17/09
11/12/09
10/26/09
3/23/10
3/22/10
DATE
REVISION
FN6728.4
FN6728.3
FN6728.2
FN6728.1
FN6728.0
Page 1, 2nd paragraph - Added “...SOT23-8 packages...” and changed “SO8” to “SOIC8”.
Also global, changed S08 to SOIC8
On page 2, Ordering Information table: Part Number ISL28213FEZ changed to ISL28213FHZ and Part
Marking changed to "TBD"
-Added Related Literature on page 1, updated ordering information by adding Eval boards.
-Added to ordering information part number ISL28213FHZ 8 Ld SOT-23 Package as coming soon.
-Replaced Figure 23 Simulated Input Noise Voltage with following changes:
Y-axis from “10 to 100” to “10,000 to 10”
Removed (A) AC sims.dat (active) from top of graph
Curve changed to improve noise performance
Made changes to Spice Net List as follows:
-Changed Revision from “C” to “D” and added improved noise performance to Revision line.
-Changed in Voltage Noise
“V_V9 29 0 .00035” to “V_V9 29 0 0.45”
“ R_R21
-Removed TC=0 in Input Stage from R_R1 through C_Cin2
-Removed TC=0 in 1st Gain Stage from R_R9 through R_R12
-Removed TC=0 in 2nd Gain Stage from R_R13 through C_C3
-Changed in Common Mode Gain Stage with Zero
“ G_G5
“ G_G6
Removed TC=0 from R_R16 through R_R23
-Changed in Pole Stage
“G_G7
“G_G8
Removed TC=0 from R_R17 through C_C5
Removed TC=0 in Output Stage with Correction Current Sources from R_R19 and R_R20
Made changes to Spice Schematic Figure 20 as follows:
-Input Stage - Modified connection to the EOS (voltage control voltage source)
-Added to Thermal Information 8 LD SOT-23 as TBD
-Added to pin configuration for the ISL28213 8 Ld SOT-23
Removed “Coming Soon” from MSOP package options in the “Ordering Information” on page 2.
Updated the Theta JA for the MSOP package option from 170°C/W to 180°C/W on page 4.
Removed “Coming Soon” from SC70 and SOT-23 package options in the “Ordering Information” on
page 2.
Changed theta Ja to 250 from 300. Added license statement (page 10) and reference in spice model
(page 12).
Initial Release
15
www.intersil.com/products
ISL28113, ISL28213, ISL28413
ISL28113, ISL28213, ISL28413
V++ 23 VG VMID 188.49e-6” to ‘G_G7
V-- 23 VG VMID 188.49e-6” to “G_G8
V++ VC VCM VMID 2.5118E-10” to “G_G5
V-- VC VCM VMID 2.5118E-10” to “G_G6
28 0 800E3 TC=0,0” to “R_R21
http://rel.intersil.com/reports/search.php
for a complete list of Intersil product families.
www.intersil.com/askourstaff
CHANGE
28 0 30”
V-- 23 VG VMID 0.18849”
V++ 23 VG VMID 0.18849”
V-- VC VCM VMID 0.25118”
V++ VC VCM VMID 0.25118”
March 25, 2010
FN6728.4