STEVAL-MKI091V1 STMicroelectronics, STEVAL-MKI091V1 Datasheet - Page 19

• Manufacturer Part Number: STEVAL-MKI091V1
• Description: DEMO BOARD FOR LIS331DLM
• Manufacturer: STMicroelectronics
• Series: MEMS, nanor

Specifications of STEVAL-MKI091V1

• Sensor Type: Accelerometer, 3 Axis
• Sensing Range: ±2g, 4g, 8g
• Interface: I²C, SPI
• Sensitivity: 64LSB/G, 32LSB/g, 16LSB/g
• Embedded: No
• Utilized Ic / Part: LIS331DLM
• Acceleration: 2 g, 4 g, 8 g
• Sensing Axis: Triple Axis
• Interface Type: I2C, SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: LIS331DLM
• Other names: 497-10491

LIS331DLM
Table 14.
5.2
Master
Slave
ST SAD+W
Table 12.
Table 13.
Transfer when Master is receiving (reading) multiple bytes of data from slave
Data are transmitted in byte format (DATA). Each data transfer contains 8 bits. The number
of bytes transferred per transfer is unlimited. Data is transferred with the Most Significant bit
(MSb) first. If a receiver can’t receive another complete byte of data until it has performed
some other function, it can hold the clock line, SCL LOW to force the transmitter into a wait
state. Data transfer only continues when the receiver is ready for another byte and releases
the data line. If a slave receiver doesn’t acknowledge the slave address (i.e. it is not able to
receive because it is performing some real time function) the data line must be left HIGH by
the slave. The Master can then abort the transfer. A LOW to HIGH transition on the SDA line
while the SCL line is HIGH is defined as a STOP condition. Each data transfer must be
terminated by the generation of a STOP (SP) condition.
In order to read multiple bytes, it is necessary to assert the most significant bit of the sub-
address field. In other words, SUB(7) must be equal to 1 while SUB(6-0) represents the
address of first register to be read.
In the presented communication format MAK is Master Acknowledge and NMAK is no
Master acknowledge.
SPI bus interface
The LIS331DLM SPI is a bus slave. The SPI allows to write and read the registers of the
device.
The serial interface interacts with the outside world with 4 wires: CS, SPC, SDI and SDO.
Master
Master
Slave
Slave
ST
SAK
ST
Transfer when master is writing multiple bytes to slave:
Transfer when master is receiving (reading) one byte of data from slave:
SAD + W
SUB
SAD + W
SAK
SAK
SR SAD+R
SAK
Doc ID 15102 Rev 4
SUB
SUB
SAK
SAK
SAK
SR
DATA
SAD + R
DATA
MAK
DATA
SAK
SAK
MAK
DATA
DATA
DATA
Digital interfaces
NMAK
SAK
NMAK
19/38
SP
SP
SP