AT91SAM7S-EK Atmel, AT91SAM7S-EK Datasheet - Page 9

• Manufacturer Part Number: AT91SAM7S-EK
• Description: KIT EVAL FOR ARM AT91SAM7S
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM7S-EK

• Contents: Evaluation Board, Parallel Cable and CD-ROM
• Processor To Be Evaluated: AT91SAM7S
• Data Bus Width: 32 bit
• Interface Type: USB
• Silicon Manufacturer: Atmel
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: AT91SAM7S
• Silicon Family Name: ARM
• Kit Contents: Board CD Docs
• For Use With/related Products: AT91SAM7S
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3.1
AT91SAM7S-EK Evaluation Board User Guide
AT91SAM7S256
Microcontroller
• Incorporates the ARM7TDMI
• 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes
• 64 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed
• Memory Controller (MC)
• Reset Controller (RSTC)
• Clock Generator (CKGR)
• Power Management Controller (PMC)
• Advanced Interrupt Controller (AIC)
• Debug Unit (DBGU)
• Periodic Interval Timer (PIT)
• Windowed Watchdog (WDT)
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– EmbeddedICE
– Single Cycle Access at Up to 30 MHz in Worst Case Conditions,
– Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10
– 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,
– Fast Flash Programming Interface for High Volume Production
– Embedded Flash Controller, Abort Status and Misalignment Detection
– Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector
– Provides External Reset Signal Shaping and Reset Source Status
– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL
– Software Power Optimization Capabilities, Including Slow Clock Mode (Down to
– Three Programmable External Clock Signals
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt
– 2-wire UART and Support for Debug Communication Channel interrupt,
– 20-bit Programmable Counter plus 12-bit Interval Counter
Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed
ms
Flash Security Bit
500 Hz) and Idle Mode
Protected
Programmable ICE Access Prevention
™
In-circuit Emulation, Debug Communication Channel Support
®
ARM
®
Thumb
Board Description
®
Processor
Section 3
6112C–ATARM–01-Feb-07
3-1