OM13000 NXP Semiconductors, OM13000 Datasheet - Page 18

• Manufacturer Part Number: OM13000
• Description: BOARD LPCXPRESSO LPC1768
• Manufacturer: NXP Semiconductors
• Type: MCUr
• Series: LPCXpressor

Specifications of OM13000

• Contents: Board
• Svhc: No SVHC (18-Jun-2010)
• Mcu Supported Families: LPC1768
• Silicon Family Name: LPC17xx
• Core Architecture: ARM
• Core Sub-architecture: Cortex - M3
• Ic Product Type: Debugger
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: LPC1768
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5101

NXP Semiconductors
7. Functional description
LPC1769_68_67_66_65_64_63
Product data sheet
7.1 Architectural overview
7.2 ARM Cortex-M3 processor
7.3 On-chip flash program memory
7.4 On-chip SRAM
7.5 Memory Protection Unit (MPU)
Remark: In the following, the notation LPC17xx refers to all parts:
LPC1769/68/67/66/65/64/63.
The ARM Cortex-M3 includes three AHB-Lite buses: the system bus, the I-code bus, and
the D-code bus (see
system bus and are used similarly to TCM interfaces: one bus dedicated for instruction
fetch (I-code) and one bus for data access (D-code). The use of two core buses allows for
simultaneous operations if concurrent operations target different devices.
The LPC17xx use a multi-layer AHB matrix to connect the ARM Cortex-M3 buses and
other bus masters to peripherals in a flexible manner that optimizes performance by
allowing peripherals that are on different slaves ports of the matrix to be accessed
simultaneously by different bus masters.
The ARM Cortex-M3 is a general purpose, 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM Cortex-M3 offers many new
features, including a Thumb-2 instruction set, low interrupt latency, hardware divide,
interruptible/continuable multiple load and store instructions, automatic state save and
restore for interrupts, tightly integrated interrupt controller with wake-up interrupt
controller, and multiple core buses capable of simultaneous accesses.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM Cortex-M3 processor is described in detail in the Cortex-M3 Technical
Reference Manual that can be found on official ARM website.
The LPC17xx contain up to 512 kB of on-chip flash memory. A new two-port flash
accelerator maximizes performance for use with the two fast AHB-Lite buses.
The LPC17xx contain a total of 64 kB on-chip static RAM memory. This includes the main
32 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and two
additional 16 kB each SRAM blocks situated on a separate slave port on the AHB
multilayer matrix.
This architecture allows CPU and DMA accesses to be spread over three separate RAMs
that can be accessed simultaneously.
The LPC17xx have a Memory Protection Unit (MPU) which can be used to improve the
reliability of an embedded system by protecting critical data within the user application.
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 6.01 — 11 March 2011
1). The I-code and D-code core buses are faster than the
LPC1769/68/67/66/65/64/63
32-bit ARM Cortex-M3 microcontroller
© NXP B.V. 2011. All rights reserved.
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