EVAL-ADUC7026QSPZ Analog Devices Inc, EVAL-ADUC7026QSPZ Datasheet - Page 13

• Manufacturer Part Number: EVAL-ADUC7026QSPZ
• Description: KIT DEV ADUC7026/7027 QUICK PLUS
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / Rohs Status: Compliant

Table 7. SPI Master Mode Timing (Phase Mode = 0)
Parameter
t
t
t
t
t
t
t
t
t
t
1
2
SL
SH
DAV
DOSU
DSU
DHD
DF
DR
SR
SF
t
t
HCLK
UCLK
depends on the clock divider or CD bits in the PLLCON MMR. t
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider; see Figure 57.
(POLARITY = 0)
(POLARITY = 1)
Description
SCLOCK low pulse width
SCLOCK high pulse width
Data output valid after SCLOCK edge
Data output setup before SCLOCK edge
Data input setup time before SCLOCK edge
Data input hold time after SCLOCK edge
Data output fall time
Data output rise time
SCLOCK rise time
SCLOCK fall time
SCLOCK
SCLOCK
MOSI
MISO
t
DOSU
t
DSU
MSB IN
1
1
MSB
t
DHD
t
SH
Figure 7. SPI Master Mode Timing (Phase Mode = 0)
t
DF
t
DAV
HCLK
2
= t
t
SL
Rev. C | Page 13 of 96
UCLK
2
t
DR
/2
BITS 6 TO 1
BITS 6 TO 1
CD
; see Figure 57.
Min
1 × t
2 × t
ADuC7019/20/21/22/24/25/26/27/28/29
UCLK
UCLK
LSB IN
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB
t
SF
HCLK
HCLK
Max
25
75
12.5
12.5
12.5
12.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns