EVAL-ADUC7026QSPZ Analog Devices Inc, EVAL-ADUC7026QSPZ Datasheet - Page 74

• Manufacturer Part Number: EVAL-ADUC7026QSPZ
• Description: KIT DEV ADUC7026/7027 QUICK PLUS
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ PLUS Kitr
• Type: MCUr

Specifications of EVAL-ADUC7026QSPZ

• Contents: Evaluation Board, Power Supply, Cable, Software, Emulator and Documentation
• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7026
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC7026
• Lead Free Status / Rohs Status: Compliant

ADuC7019/20/21/22/24/25/26/27/28/29
Table 138. I2CxDIV Registers
Name
I2C0DIV
I2C1DIV
I2CxDIV are the clock divider registers.
Table 139. I2CxIDx Registers
Name
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
I2CxID0, I2CxID1, I2CxID2, and I2CxID3 are slave address
device ID registers of I2Cx.
Table 140. I2CxCCNT Registers
Name
I2C0CCNT
I2C1CCNT
I2CxCCNT are 8-bit start/stop generation counters. They hold
off SDA low for start and stop conditions.
Table 141. I2CxFSTA Registers
Name
I2C0FSTA
I2C1FSTA
I2CxFSTA are FIFO status registers.
Address
0xFFFF0830
0xFFFF0930
Address
0xFFFF0838
0xFFFF083C
0xFFFF0840
0xFFFF0844
0xFFFF0938
0xFFFF093C
0xFFFF0940
0xFFFF0944
Address
0xFFFF0848
0xFFFF0948
Address
0xFFFF084C
0xFFFF094C
0x1F1F
0x1F1F
Default Value
Default Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Default Value
0x01
0x01
Default Value
0x0000
0x0000
Access
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
Access
R/W
R/W
Rev. C | Page 74 of 96
Table 142. I2C0FSTA MMR Bit Descriptions
Bit
15:10
9
8
7:6
5:4
3:2
1:0
Access
Type
R/W
R/W
R
R
R
R
Value
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
Description
Reserved.
Master transmit FIFO flush. Set by the
user to flush the master Tx FIFO.
Cleared automatically when the
master Tx FIFO is flushed. This bit
also flushes the slave receive FIFO.
Slave transmit FIFO flush. Set by the
user to flush the slave Tx FIFO. Cleared
automatically after the slave Tx FIFO
is flushed.
Master Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Master Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Rx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.
Slave Tx FIFO status bits.
FIFO empty.
Byte written to FIFO.
One byte in FIFO.
FIFO full.