STM8/128-EVAL STMicroelectronics, STM8/128-EVAL Datasheet - Page 79

• Manufacturer Part Number: STM8/128-EVAL
• Description: BOARD EVAL FOR STM8S
• Manufacturer: STMicroelectronics
• Type: MCUr

Specifications of STM8/128-EVAL

• Mfg Application Notes: STM8S Getting Started
• Contents: Evaluation Board
• Silicon Manufacturer: ST Micro
• Core Architecture: STM8
• Core Sub-architecture: STM8
• Silicon Core Number: STM8
• Silicon Family Name: STM8S2xx
• Kit Contents: Board
• For Use With/related Products: STM8S2xx
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8506

STM8S207xx, STM8S208xx
10.3.8
Table 42.
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
t
t
t
t
dis(SO)
t
w(SCKH)
t
w(SCKL)
a(SO)
1/t
su(NSS)
t
Symbol
t
t
t
h(NSS)
t
t
t
su(MI)
t
v(SO)
h(MO)
su(SI)
v(MO)
h(SO)
t
h(MI)
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(1)(2)
(1)
(1)(3)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
SPI serial peripheral interface
Unless otherwise specified, the parameters given in
performed under ambient temperature, f
conditions. t
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
SPI characteristics
SPI clock frequency
SPI clock rise and fall time
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
MASTER
= 1/f
MASTER
Slave mode
Master mode
Slave mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Master mode
Slave mode
Master mode
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Doc ID 14733 Rev 11
.
Conditions
MASTER
frequency and V
Table 42
4 x t
t
SCK
are derived from tests
Min
MASTER
70
10
25
31
12
/2 - 15
0
5
5
7
DD
0
Electrical characteristics
supply voltage
t
3 x t
SCK
Max
10
25
/2 + 15
MASTER
75
30
6
79/105
Unit
MHz
ns