CY3684 Cypress Semiconductor Corp, CY3684 Datasheet - Page 23

• Manufacturer Part Number: CY3684
• Description: KIT DEVELOPMENT EZ-USB FX2LP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FXr
• Type: MCUr

Specifications of CY3684

• Contents: 2 Boards, Cables, CD
• Silicon Manufacturer: Cypress
• Application Sub Type: USB
• Kit Application Type: Interface
• Silicon Core Number: CY7C68013A-128AXC
• Features: FX2LP Development Kit
• Silicon Family Name: EZ-USB FX2LP
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: CY7C68013A-128AC, CY7C64713-128AC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1677; CY3684; Q2204408

6.0
EZ-USB Development Board
MODULE fx2lp
" Swapped dipswitch settings 00 and 10 on 4-3-98 to allow the all-switch-
on default
"Inputs
"Outputs
modesw = [mm1,mm0];
addr = [A15,A14,A13,A12,A11,nRD];" high nibble of the address bus + RD
equations
" The 3681 board turns PF0 on at 0x80xx reads and off at 0x81xx reads.
" This board turns PF0 on at 0x8xxx reads and off at 0x88xx reads.
PF0.S = (addr == ^b100000);
PF0.R = (addr == ^b100010);
PF0.CLK = CLKOUT;
PF1.S = (addr == ^b100100);
PF1.R = (addr == ^b100110);
PF1.CLK = CLKOUT;
PF2.S = (addr == ^b101000);
PF2.R = (addr == ^b101010);
PF2.CLK = CLKOUT;
PF3.S = (addr == ^b101100);
PF3.R = (addr == ^b101110);
PF3.CLK = CLKOUT;
WHEN
{
nRAMCE =
nRAMOE=
EA =
}
ELSE WHEN(modesw == 01) THEN" Ext P&D mem at 8000 (can add mem to 0-8K)
{
!nRAMCE=
!nRAMOE=
EA =
}
ELSE WHEN(modesw == 11) THEN" Ext P&D mem at 0000 and 8000
{
!nRAMCE = 1;
x,c,z = .X.,.C.,.Z.;
A12,A13,A14,A15
A11
nRD,nPSEN,CLKOUT
mm1,mm0
EA,nRAMOE,nRAMCE
PF0,PF1,PF2,PF3
Appendix A: U2 (GAL) code (file is 'FX2LP.ABL')
(modesw == 00) THEN" No external memory
1;
1;
0;
A15;
!nRD # !nPSEN;" Combine program & data memory
0;
pin 11,12,13,16;
pin 4;
pin 6,5,2;
pin 9,7;
pin 21,25,27;
pin 17,18,19,20 istype 'reg_sr';
" two dipswitches
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