C8051F330DK Silicon Laboratories Inc, C8051F330DK Datasheet - Page 167
![DEV KIT FOR C8051F330/F331](/photos/9/23/92306/c8051f330dk_sml.jpg)
C8051F330DK
Manufacturer Part Number
C8051F330DK
Description
DEV KIT FOR C8051F330/F331
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F330DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F33x
Interface Type
RS-232
Operating Supply Voltage
7 V to 15 V
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F330
Silicon Family Name
C8051F33x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051F330, C8051F331
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1264
- Current page: 167 of 210
- Download datasheet (2Mb)
Bit 7:
Bit 6:
Bit 5:
Bit 4:
Bits 3 – 2: NSSMD1 – NSSMD0: Slave Select Mode.
Bit 1:
Bit 0:
SPIF
R/W
Bit7
SPIF: SPI0 Interrupt Flag.
This bit is set to logic 1 by hardware at the end of a data transfer. If interrupts are enabled,
setting this bit causes the CPU to vector to the SPI0 interrupt service routine. This bit is not
automatically cleared by hardware. It must be cleared by software.
WCOL: Write Collision Flag.
This bit is set to logic 1 by hardware if a write to SPI0DAT is attempted when the transmit
buffer has not been emptied to the SPI shift register. It must be cleared by software.
MODF: Mode Fault Flag.
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when a master mode
collision is detected (NSS is low, MSTEN = 1, and NSSMD[1:0] = 01). This bit is not auto-
matically cleared by hardware. It must be cleared by software.
RXOVRN: Receive Overrun Flag (Slave Mode only).
This bit is set to logic 1 by hardware (and generates a SPI0 interrupt) when the receive buf-
fer still holds unread data from a previous transfer and the last bit of the current transfer is
shifted into the SPI0 shift register. This bit is not automatically cleared by hardware. It must
be cleared by software.
Selects between the following NSS operation modes:
(See
Slave Mode Operation” on page 167
00: 3-Wire Slave or 3-wire Master Mode. NSS signal is not routed to a port pin.
01: 4-Wire Slave or Multi-Master Mode (Default). NSS is always an input to the device.
1x: 4-Wire Single-Master Mode. NSS signal is mapped as an output from the device and will
assume the value of NSSMD0.
TXBMT: Transmit Buffer Empty.
This bit will be set to logic 0 when new data has been written to the transmit buffer. When
data in the transmit buffer is transferred to the SPI shift register, this bit will be set to logic 1,
indicating that it is safe to write a new byte to the transmit buffer.
SPIEN: SPI0 Enable.
This bit enables/disables the SPI.
0: SPI disabled.
1: SPI enabled.
WCOL
R/W
Bit6
Section “17.2. SPI0 Master Mode Operation” on page 165
SFR Definition 17.2. SPI0CN: SPI0 Control
MODF
R/W
Bit5
RXOVRN NSSMD1 NSSMD0
R/W
Bit4
Rev. 1.7
).
R/W
Bit3
R/W
Bit2
C8051F330/1/2/3/4/5
TXBMT
Bit1
R
and
SFR Address: 0xF8
Section “17.3. SPI0
SPIEN
R/W
Bit0
00000110
Addressable
Reset Value
Bit
171
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