C8051F700DK Silicon Laboratories Inc, C8051F700DK Datasheet - Page 13

DEV KIT FOR C8051F700

C8051F700DK

Manufacturer Part Number
C8051F700DK
Description
DEV KIT FOR C8051F700
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F700DK

Contents
Board, Cables, CD, Debugger, Power Supply
Processor To Be Evaluated
C8051F7x
Processor Series
C8051F7xx
Interface Type
USB
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051F7xx
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1635
6.8. Voltage Reference (VREF) and Analog Ground Connectors (J13 and J14)
The VREF connector can be used to connect the VREF pin from the MCU (P0.0) to external 0.1 uF and 4.7 uF
decoupling capacitors. The C8051F700 device is connected to the capacitors through the J13 header. The AGND
pin from the MCU (P0.1) can be connected to the board digital ground through the J14 header.
6.9. Potentiometer (J16)
The C8051F700 device has the option to connect port pin P1.2 to a 10 k linear potentiometer. The potentiometer
is connected through the J16 header. The potentiometer can be used for testing the analog-to-digital (ADC)
converter of the MCU.
6.10. C2 Pin Sharing
On the C8051F700, the debug pin C2CK is shared with the /RST pin. The target board includes the resistor
necessary to enable pin sharing which allows the pin–shared /RST to be used normally while simultaneously
debugging the device. See Application Note “AN124: Pin Sharing Techniques for the C2 Interface” at
www.silabs.com
for more information regarding pin sharing.
Header Pins
J12[9-10]
J12[1-2]
J12[3-4]
J12[5-6]
J12[7-8]
Table 4. Serial Interface Header (J12) Description
MCU I/O Pin
none
P0.5
P0.4
P0.6
P0.7
Rev. 0.2
Board VDD to CP2103 VIO
CP2103 Pin
/RTS
/CTS
RXD
TXD
C8051F700-DK
13

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