C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 130

• Manufacturer Part Number: C8051T610DK
• Description: KIT DEV FOR C8051T61X MCU'S
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T610DK

• Contents: Board, daughter boards, power adapter, cables, documentation and software
• Processor To Be Evaluated: C8051T61x
• Interface Type: USB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: C8051T610
• For Use With: 336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1443

C8051T610/1/2/3/4/5/6/7
SFR Definition 21.14. P2SKIP: Port 2 Skip
SFR Address = 0xD6
SFR Definition 21.15. P3: Port 3
SFR Address = 0xB0; Bit-Addressable
130
Note: Only P2.0-P2.3 are associated with the crossbar.
Note: P3.1-P3.4 are not connected to external pins on the C8051T611/3/5 and C8051T616/7 devices.
Name
Reset
Name
Reset
7:4
3:0
7:5
4:0
Bit
Bit
Type
Type
Bit
Bit
Unused
P2SKIP[3:0]
P3[4:0]
Name
Unused
Name
R
7
0
7
0
Unused. Read = 000b; Write = Don’t Care.
Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Unused. Read = 0000b; Write = Don’t Care.
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R
6
0
6
0
Description
R
R
5
0
5
0
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
Rev 1.0
4
0
4
1
Function
Write
3
0
3
1
P3[4:0]
R/W
2
0
2
1
P2SKIP[3:0]
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
R/W
1
0
1
1
Read
0
0
0
1