C8051T610DK Silicon Laboratories Inc, C8051T610DK Datasheet - Page 88
![KIT DEV FOR C8051T61X MCU'S](/photos/9/23/92350/c8051t610dk_sml.jpg)
C8051T610DK
Manufacturer Part Number
C8051T610DK
Description
KIT DEV FOR C8051T61X MCU'S
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051T610DK
Contents
Board, daughter boards, power adapter, cables, documentation and software
Processor To Be Evaluated
C8051T61x
Interface Type
USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
C8051T610
For Use With
336-1507 - DAUGHTER BOARD T610 24QFN SOCKET336-1506 - DAUGHTER BOARD T610 28QFN SOCKET336-1505 - DAUGHT BOARD T610 32TQFP SOCKET
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1443
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C8051T610/1/2/3/4/5/6/7
SFR Definition 16.1. IE: Interrupt Enable
SFR Address = 0xA8; Bit-Addressable
88
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
ESPI0
Name
ES0
EX1
EX0
ET2
ET1
ET0
EA
R/W
EA
7
0
Enable All Interrupts.
Globally enables/disables all interrupts. It overrides individual interrupt mask settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Enable Serial Peripheral Interface (SPI0) Interrupt.
This bit sets the masking of the SPI0 interrupts.
0: Disable all SPI0 interrupts.
1: Enable interrupt requests generated by SPI0.
Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable Timer 2 interrupt.
1: Enable interrupt requests generated by the TF2L or TF2H flags.
Enable UART0 Interrupt.
This bit sets the masking of the UART0 interrupt.
0: Disable UART0 interrupt.
1: Enable UART0 interrupt.
Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupt.
1: Enable interrupt requests generated by the TF1 flag.
Enable External Interrupt 1.
This bit sets the masking of External Interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 input.
Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupt.
1: Enable interrupt requests generated by the TF0 flag.
Enable External Interrupt 0.
This bit sets the masking of External Interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the INT0 input.
ESPI0
R/W
6
0
R/W
ET2
5
0
R/W
ES0
Rev 1.0
4
0
Function
R/W
ET1
3
0
EX1
R/W
2
0
R/W
ET0
1
0
R/W
EX0
0
0
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